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AK5701KN_17 Datasheet, PDF (40/64 Pages) Asahi Kasei Microsystems – PLL & MIC-AMP内蔵16-Bit Stereo ADC | |||
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[AK5701]
â ã·ãªã¢ã«ã³ã³ããã¼ã«ã¤ã³ã¿ãã§ã¼ã¹
ã¬ã¸ã¹ã¿è¨å®ã¯3ç·å¼ã·ãªã¢ã«I/Fãã³(CSN, CCLK, CDTI)ã§æ¸ãè¾¼ã¿ãè¡ãã¾ããCSP pinã®è¨å®ã«ããCSN
pinã®æ¥µæ§ã¨Chip addressãåãæ¿ããã¾ãã
1) CSP pin = âLâã®ã¨ã
I/Fä¸ã®ãã¼ã¿ã¯Chip address (2bits, â10âåºå®), Read/Write (1bit, â1âåºå®), Register address (MSB first, 5bits) ã¨
Control Data (MSB first, 8bits)ã§æ§æããã¾ãããã¼ã¿éä¿¡å´ã¯CCLKã® âï¯âã§åããããåºåããåä¿¡å´ã¯ âïâ
ã§åãè¾¼ã¿ã¾ãããã¼ã¿ã®æ¸ãè¾¼ã¿ã¯CSNã® âï¯âå¾16åç®ã®CCLK âïâã§æå¹ã«ãªãã¾ãã1ã¢ãã¬ã¹ã¸ã®æ¸
ãè¾¼ã¿æ¯ã«CSNãä¸åº¦ âHâã«ãã¦ãã ãããCCLKã®ã¯ããã¯ã¹ãã¼ãã¯7MHz (max)ã§ããPDN pin = âLâã§
ã¬ã¸ã¹ã¿ã®å¤ã¯ãªã»ããããã¾ãã
CSN
CCLK
CDTI
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Clock, âHâ or âLâ
Clock, âHâ or âLâ
âHâ or âLâ
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
âHâ or âLâ
C1-C0:
R/W:
A4-A0:
D7-D0:
Chip Address (C1 = â1â, C0 = CAD0) ; Fixed to â10â
READ/WRITE (â1â: WRITE, â0â: READ); Fixed to â1â
Register Address
Control data
Figure 41. ã·ãªã¢ã«ã³ã³ããã¼ã«ã¤ã³ã¿ãã§ã¼ã¹ã¿ã¤ãã³ã°(CSP pin = âLâ)
2) CSP pin = âHâã®ã¨ã
I/Fä¸ã®ãã¼ã¿ã¯Chip address (2bits, â01âåºå®), Read/Write (1bit, â1âåºå®), Register address (MSB first, 5bits) ã¨
Control Data (MSB first, 8bits)ã§æ§æããã¾ãããã¼ã¿éä¿¡å´ã¯CCLKã® âï¯âã§åããããåºåããåä¿¡å´ã¯ âïâ
ã§åãè¾¼ã¿ã¾ãããã¼ã¿ã®æ¸ãè¾¼ã¿ã¯CSNã® âïâå¾16åç®ã®CCLK âïâã§æå¹ã«ãªãã¾ãã1ã¢ãã¬ã¹ã¸ã®æ¸
ãè¾¼ã¿æ¯ã«CSNãä¸åº¦ âLâã«ãã¦ãã ãããCCLKã®ã¯ããã¯ã¹ãã¼ãã¯7MHz (max)ã§ããPDN pin = âLâã§
ã¬ã¸ã¹ã¿ã®å¤ã¯ãªã»ããããã¾ãã
CSN
CCLK
CDTI
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Clock, âHâ or âLâ
Clock, âHâ or âLâ
âHâ or âLâ
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
âHâ or âLâ
C1-C0:
R/W:
A4-A0:
D7-D0:
Chip Address (C1 = â0â, C0 = CAD1) ; Fixed to â01â
READ/WRITE (â1â: WRITE, â0â: READ); Fixed to â1â
Register Address
Control data
Figure 42. ã·ãªã¢ã«ã³ã³ããã¼ã«ã¤ã³ã¿ãã§ã¼ã¹ã¿ã¤ãã³ã°(CSP pin = âHâ)
MS0404-J-04
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2015/10
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