AK5701KN_17 Datasheet, PDF (31/64 Pages) Asahi Kasei Microsystems – PLL & MIC-AMP内蔵16-Bit Stereo ADC

[AK5701]
LRCK
15 0 1 2 8 8 9 10 11 12 13 14 15 0 1 2 8 8 9 10 11 12 13 14 15 0
BCLK(32fs)
Lch
Rch
SDTO(o)
0 15 14 ⁸ 8 7 6 5 4 3 2 1 0 15 14 ⁸ 8 7 6 5 4 3 2 1 0
31
BCLK(64fs)
SDTO(o)
0 1 2 8 14 15 16 17 18 29 30 31
Lch
15 14 ⁸ 2 1 0
0 1 2 8 14 15 16 17 18 13 30 31
Rch
15 14 ⁸ 2 1 0
1/fs
15:MSB, 0:LSB
Figure 30. Mode 1 Timing (BCKP = “0”, MSBS = “0”, M/S = “1”)
LRCK
15 0 1 2 8 8 9 10 11 12 13 14 15 0 1 2 8 8 9 10 11 12 13 14 15 0
BCLK(32fs)
Lch
Rch
SDTO(o)
0 15 14 ⁸ 8 7 6 5 4 3 2 1 0 15 14 ⁸ 8 7 6 5 4 3 2 1 0
31
BCLK(64fs)
SDTO(o)
0 1 2 8 14 15 16 17 18 29 30 31
Lch
15 14 ⁸ 2 1 0
0 1 2 8 14 15 16 17 18 13 30 31
Rch
15 14 ⁸ 2 1 0
1/fs
15:MSB, 0:LSB
Figure 31. Mode 1 Timing (BCKP = “1”, MSBS = “0”, M/S = “1”)
LRCK
15 0 1 2 8 8 9 10 11 12 13 14 15 0 1 2 8 8 9 10 11 12 13 14 15 0
BCLK(32fs)
Lch
Rch
SDTO(o)
0 15 14 ⁸ 8 7 6 5 4 3 2 1 0 15 14 ⁸ 8 7 6 5 4 3 2 1 0
31
BCLK(64fs)
SDTO(o)
0 1 2 8 14 15 16 17 18 29 30 31
Lch
15 14 ⁸ 2 1 0
0 1 2 8 14 15 16 17 18 13 30 31
Rch
15 14 ⁸ 2 1 0
1/fs
15:MSB, 0:LSB
Figure 32. Mode 1 Timing (BCKP = “0”, MSBS = “1”, M/S = “1”)
LRCK
15 0 1 2 8 8 9 10 11 12 13 14 15 0 1 2 8 8 9 10 11 12 13 14 15 0
BCLK(32fs)
Lch
Rch
SDTO(o)
0 15 14 ⁸ 8 7 6 5 4 3 2 1 0 15 14 ⁸ 8 7 6 5 4 3 2 1 0
31
BCLK(64fs)
SDTO(o)
0 1 2 8 14 15 16 17 18 29 30 31
Lch
15 14 ⁸ 2 1 0
0 1 2 8 14 15 16 17 18 13 30 31
Rch
15 14 ⁸ 2 1 0
1/fs
15:MSB, 0:LSB
Figure 33. Mode 1 Timing (BCKP = “1”, MSBS = “1”, M/S = “1”)
MS0404-J-04
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2015/10