AK5701KN_17 Datasheet, PDF (37/64 Pages) Asahi Kasei Microsystems – PLL & MIC-AMP内蔵16-Bit Stereo ADC

[AK5701]
3. ALC動作設定手順例
Table 28は、録音パスの場合のALC設定例です。
Register Name
LMTH
ZELMN
ZTM1-0
WTM1-0
REF7-0
IVL7-0,
IVR7-0
LMAT1-0
RGAIN1-0
ALC
Comment
fs=8kHz
Data
Operation
Limiter detection Level
01
4.1dBFS
Limiter zero crossing detection
0
Enable
Zero crossing timeout period
00
16ms
Recovery waiting period
*WTM1-0 bits should be the same data 00
16ms
as ZTM1-0 bits
Maximum gain at recovery operation E1H
+30dB
Gain of IVOL
91H
0dB
Limiter ATT step
Recovery GAIN step
ALC enable
00
00
1
Table 28. ALC設定例
1 step
1 step
Enable
fs=44.1kHz
Data
Operation
01
4.1dBFS
0
Enable
10
11.6ms
10
11.6ms
E1H
+30dB
91H
0dB
00
1 step
00
1 step
1
Enable
ALC動作中は、以下のビットへの変更を禁止します。これらのビットを変更する場合は、ALC動作を終了(ALC
bit = “0”またはPMADL = PMADR bits = “0”)してから行って下さい。
・LMTH, LMAT1-0, WTM1-0, ZTM1-0, RGAIN1-0, REF7-0, ZELMNの各ビット
Manual Mode
Example:
Limiter = Zero crossing Enable
Recovery Cycle = 16ms@8kHz
Limiter and Recovery Step = 1
Maximum Gain = +30.0dB
Limiter Detection Level = 4.1dBFS
ALC bit = “1”
WR (IVL/R7-0) ^{* The value of IVOL should be}
the same or smaller than REF’s
WR (ZTM1-0, WTM1-0)
(1) Addr=18H&19H, Data=91H
(2) Addr=1AH, Data=00H
WR (REF7-0)
(3) Addr=1BH, Data=E1H
WR (LMAT1-0, RGAIN1-0, ZELMN, LMTH1-0; ALC= “1”)
(4) Addr=1CH, Data=81H
ALC Operation
Note : WR : Write
Figure 39. ALC動作設定手順例
MS0404-J-04
- 37 -
2015/10