HMC704LP4E Datasheet, PDF (43/44 Pages) Hittite Microwave Corporation – 8 GHz fractionaL-N PLL

v04.0215
HMC704LP4E
8 GHZ FRACTIONAL-N PLL
Table 25. Reg 0Ch Exact Frequency Register
BIT
TYPE
NAME
W DEFLT
[13:0]
R/W
Number of Channels per Fpd 14
0
DESCRIPTION
Comparison Frequency divided by the channel spacing. Must be an
integer. Frequencies at multiples of the channel spacing will have
zero frequency error. Only works in modulator Mode B. Must be 0
otherwise
0: Disabled
1: Disabled
2 to 16383d (3FFFh) allowed
Table 26. Reg 0Fh GPO Register
BIT
TYPE
NAME
[4:0]
R/W
gpo_select
[5]
R/W
[6]
R/W
[7]
R/W
[8]
R/W
[9]
R/W
GPO Test Data
Prevent Automux SDO
Prevent Driver Disable
Disable PFET
Disable NFET
W DEFLT
DESCRIPTION
Signal selected here is output to SDO pin when enabled
0. Data from Reg0F[5]
1. Lock Detect Output
2. Lock Detect Trigger
3: Lock Detect Window Output
4: Ring Osc Test
5. Pullup Hard from CSP
6. PullDN hard from CSP
7. Reserved
8: Reference Buffer Output
9: Ref Divider Output
10. VCO divider Output
11. Modulator Clock from VCO divider
12. Auxiliary Clock
5
1
13. Aux SPI Clock
14. Aux SPI Enable
15. Aux SPI Data Out
16. PD DN
17. PD UP
18. SD3 Clock Delay
19. SD3 Core Clock
20. AutoStrobe Integer Write
21. Autostrobe Frac Write
22. Autostrobe Aux SPI
23. SPI Latch Enable
24. VCO Divider Sync Reset
25. Seed Load Strobe
26.-29 Not Used
30. SPI Output Buffer En
31. Soft RSTB
1
0
1 - GPO Test Data when GPO_Select = 0
1
0
1- inhibits Automux of the SPI SDO line with Lock Detect
1
0
1- Prevents SPI from disabling SDO. Should be 1 if using HMC SPI
mode.
1
0
Disable PFET
1
0
Disable NFET
5 - 43
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