HMC704LP4E Datasheet, PDF (38/44 Pages) Hittite Microwave Corporation – 8 GHz fractionaL-N PLL

v04.0215
HMC704LP4E
8 GHZ FRACTIONAL-N PLL
Table 19. Reg 06h SD CFG Register
BIT
TYPE
NAME
W
[1:0]
R/W
Seed select
2
[3:2]
R/W
Modulator order
2
[6:4]
R/W
Reserved
3
[7]
R/W
frac_bypass
1
[8]
R/W
Autoseed
1
[9]
R/W
clkrq_refdiv_sel
1
[10]
R/W
Modulator Core Clk Select
1
[11]
R/W
frac_rstb
1
[12]
R/W
Reserved
1
[13]
R/W
Spare
1
[15:14]
R/W
Reserved
2
[17:16]
R/W
Reserved
2
[18]
R/W
BIST Enable
1
[20:19] R/W
RDIV BIST Cycles
2
[21]
R/W
Reserved
1
[22]
R/W
Reserved
1
DEFLT
2
2
7
0
1
1
0
1
0
0
0
0
0
0
0
0
DESCRIPTION
Selects the Seed in Fractional Mode
00: 0 seed
01: lsb seed
02: B29D08h seed
03: 50F1CDh seed
Note: Writes to this register are stored in the PLL and are only
loaded into the modulator when a frequency change is executed
and if autoseed Reg06h[8] =1
Select the Delta Sigma Modulator Type
0: Reserved
1: Reserved
2: Mode B Offers better out of band spectral performance. Mode B
Required for Exact Frequency Mode.
3: Mode A Offers better in band spectral performance
Program 100b
0: Use Modulator, Required for Fractional Mode,
1: Bypass Modulator, Required for Integer Mode
Note: In bypass fractional modulator output is ignored, but frac-
tional modulator continues to be clocked if frac_rstb =1, Can be
used to test the isolation of the digital fractional mod­ulator from the
VCO output in integer mode
1: Loads the modulator seed (start phase) whenever the frac
register is written
0: When frac register write changes frequency, modulator starts
with previous contents
Selects the modulator core clock source- for Test Only
1: VCO divider clock (Recommended for normal operation)
0: Ref divider clock
Ignored if bits [10] or [21] are set
0: Modulator auxclk
1: Modulator VCO Clock delay (Recommended)
0: Disable Modulator, use for Integer Mode or Integer Mode with
CSP
1: Enable Modulator Core, required for Fractional Mode, or Integer
isolation testing
Program 0
Don’t care
Program 00b
Program 11b for PFD rates > = 50 MHz and 00b for <50 MHz when
using Modulator Order Mode A (Reg06h[3:2]=11b). When using
Modulator Order Mode B (Reg06h[3:2]=10b), bits [17:16] are don’t
care bits
Enable Built in Self Test. Program 0 for normal operation
Program 00b
0:1023
1:2047
2:3071
3:4095
Program 0
Program 0
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Trademarks and registered tradem_Aar_pks_par_le_icth_ae_tp_ir_oop_ner_sty_uof_pth_pei_or r_re_ts_:pe_Pct_hive_oo_nw_ene_:rs₉. _{78-250-3343 o}A_rpp_Rli_Fca_Mtio_Gn_-S_au_pp_pp_sor_@t:_aP_nho_an_loe:_g1_.-_c8_o0_m0-ANALOG-D
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