HMC704LP4E Datasheet, PDF (16/44 Pages) Hittite Microwave Corporation – 8 GHz fractionaL-N PLL

v04.0215
HMC704LP4E
8 GHZ FRACTIONAL-N PLL
It should be noted that actual phase noise near the corner frequency of the loop bandwidth is affected by loop parame-
ters and one should use a more complete design tool such as Hittite PLL Design for better esti­mates of the phase noise
performance. Noise models for each of the components in Hittite PLL Design can be derived from the FOM equations
or can be provided by Hittite applications engineering.
Spurious Performance
Integer Operation
The VCO always operates at an integer multiple of the PD frequency in an integer PLL. In general spurious signals
originating from an integer PLL can only occur at multiples of the PD frequency. These unwanted outputs are often sim-
ply referred to as reference sidebands.
Spurs unrelated to the reference frequency must originate from outside sources. External spurious sources can modu-
late the VCO indirectly through power supplies, ground, or output ports, or bypass the loop filter due to poor isolation of
the filter. It can also simply add to the output of the PLL.
The HMC704LP4E has been designed and tested for ultra-low spurious performance. Reference spuri­ous levels are
typically below -100 dBc with a well designed board layout. A regulator with low noise and high power supply rejection,
such as the HMC860LP3E, is recommended to minimize external spurious sources.
Reference spurious levels of below -100 dBc require superb board isolation of power supplies, isolation of the VCO
from the digital switching of the PLL and isolation of the VCO load from the PLL. Typical board layout, regulator design,
demo boards and application information are available for very low spurious operation. Operation with lower levels of
isolation in the application circuit board, from those rec­ommended by Hittite, can result in higher spurious levels.
Of course, if the application environment contains other interfering frequencies unrelated to the PD fre­quency, and if
the application isolation from the board layout and regulation are insufficient, then the unwanted interfering frequencies
will mix with the desired PLL output and cause additional spurs. The level of these spurs is dependant upon isolation
and supply regulation or rejection (PSRR).
Fractional Operation
Unlike an integer PLL, spurious signals in a fractional PLL can occur due to the fact that the VCO operates at frequen-
cies unrelated to the PD frequency. Hence intermodulation of the VCO and the PD harmonics can cause spurious side-
bands. Spurious emissions are largest when the VCO operates very close to an integer multiple of the PD. When the
VCO operates exactly at a harmonic of the PD then, no in-close mixing products are present.
Interference is always present at multiples of the PD frequency, f_pd, and the VCO frequency, f_vco. If the fractional mode
of operation is used, the difference, Δ, between the VCO frequency and the nearest har­monic of the reference, will cre-
ate what are referred to as integer boundary spurs. Depending upon the mode of operation of the PLL, higher order,
lower power spurs may also occur at multiples of integer fractions (sub-harmonics) of the PD frequency. That is, frac-
tional VCO frequencies which are near nf_pd + f_pdd/m, where n, d and m are all integers and d<m (mathematicians refer
to d/m as a rational num­ber). We will refer to f_pdd/m as an integer fraction. The denominator, m, is the order of the spuri-
ous product. Higher values of m produce smaller amplitude spurious at offsets of mΔ and usually when m>4 spurs are
very small or unmeasurable.
The worst case, in fractional mode, is when d=0, and the VCO frequency is offset from nf_pd by less than the loop band-
width. This is the “in-band fractional boundary” case.
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