HMC704LP4E Datasheet, PDF (13/44 Pages) Hittite Microwave Corporation – 8 GHz fractionaL-N PLL

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HMC704LP4E
8 GHZ FRACTIONAL-N PLL
Theory of Operation
The PLL consists of the following functional blocks:
1. Reference Path Input Buffer and ’R’ Divider
2. VCO Path Input Buffer, RF Divide-by-2 and Multi-Modulus ’N’ Divider
3. Δ Σ Fractional Modulator
4. Phase Detector
5. Charge Pump
6. Main Serial Port
7. Lock Detect and Register Control
8. Auxiliary Output Serial Port
9. Power On Reset Circuit
External VCO
The PLL charge pump can operate with the charge pump supply as high as 5.2V. The charge pump output at the varac-
tor tuning port, normally can maintain low noise performance to within 500 mV of ground or 800 mV of the upper supply
voltage.
Figure 23. Synthesizer with External VCO
High Performance Low Spurious Operation
The HMC704LP4E has been designed for the best phase noise and low spurious content possible in an integrated PLL.
Spurious signals in a PLL can occur in any mode of operation and can come from a number of sources.
Figure of Merit Noise Floor and Flicker Noise Models
The phase noise of an ideal phase locked oscillator is dependent upon a number of factors:
a. Frequency of the VCO, and the Phase detector
b. VCO Sensitivity, kvco, VCO and Reference Oscillator phase noise profiles
c. Charge Pump current, Loop Filter and Loop Bandwidth
d. Mode of Operation: Integer, Fractional modulator style
The contributions of the PLL to the output phase noise can be characterized in terms of a Figure of Merit (FOM) for both
the PLL noise floor and the PLL flicker (1/f) noise regions, as follows:
5 - 13
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