HMC704LP4E Datasheet, PDF (22/44 Pages) Hittite Microwave Corporation – 8 GHz fractionaL-N PLL

v04.0215
HMC704LP4E
8 GHZ FRACTIONAL-N PLL
Analog Window Lock Detect
The lock detect window may be generated by either an analog circuit or a digital one-shot circuit. Clearing “Reg
07h”[6]=0 will result in a fixed, analog, nominal 10 nsec window, as shown in Figure 31. The analog window cannot be
used if the PD rate is very high, for example near 100 MHz, or if the charge pump offset current results in an offset larger
than 7 nsec.
For example a 25 MHz PD rate with a 1mA charge pump setting (“Reg 09h”[6:0]=”Reg 09h”[13:7]= 50d) and a -400uA
offset current “Reg 09h”[20:14]=80d), would have a phase offset of about 400/1000 = 40% of the PD period or about
16 nsec. In such an extreme case the divided VCO would arrive 16 ns after the PD ref­erence, and would always arrive
outside of the 10 nsec lock detect window. In such a case the lock detect circuit would always read unlocked, even
though the VCO might be locked. The charge pump current, reference period, charge pump offset current, and lock
detect win­dow are related.
Digital Window Lock Detect
Setting “Reg 07h”[6]=1 will result in a variable length lock detect window based upon the internal digital timer. The one
shot timer period is controlled by “Reg 07h”[11:10]. The resulting lock detect window period is then generated by the
number of timer periods defined in “Reg 07h”[9:7].
Declaration of Lock
“Reg 07h”[2:0] defines the number of consecutive counts of the divided VCO that must land inside the lock detect win-
dow to declare lock. If for example we set “Reg 07h”[2:0] =5 then the VCO arrival would have to occur inside the widow
2048 times in a row to be declared locked, which would result in a Lock Detect Flag high. A single occurrence outside of
the window will result in an out of lock, i.e. Lock Detect Flag low. Once low, the Lock Detect Flag will stay low until the
lkd_wincnt_max = 2048 condition is met again.
The Lock Detect Flag status is always readable in “Reg 12h”[1]. Lock Detect status is also output to the LD_SDO pin if
“Reg 0Fh”[4:0]=1, “Reg 0Fh”[6]=1 and “Reg 0Fh”[7]=1. Clearing”Reg 0Fh”[6]=0 will display the Lock Detect Flag on
LD_SDO except when a serial port read is requested, in which case the pin reverts temporarily to the Serial Data Out
pin and returns to the Lock Detect Flag after the read is completed. Timing of the Lock Detect function is shown in
Figure 31 and Figure 32.
LOCK
DETECT
WINDOW
Twindow = 10nsec
LOCK WINDOW
50MHz PD
VCO with Jitter
PHASE JITTER
PHASE JITTER
AVG PHASE OFFSET ~ 0
INTEGER MODE
AVG PHASE OFFSET ~ 0
INTEGER MODE
Figure 31. Normal Lock Detect Window - Integer Mode, Zero Offset
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