HMC704LP4E Datasheet, PDF (32/44 Pages) Hittite Microwave Corporation – 8 GHz fractionaL-N PLL

v04.0215
HMC704LP4E
8 GHZ FRACTIONAL-N PLL
HMC Mode - Serial Port READ Operation
A typical HMC Mode READ cycle is shown in Figure 37.
a. The Master (host) asserts both SEN (Serial Port Enable) and SDI to indicate a READ cycle, followed
by a rising edge SCLK. Note: The Lock Detect (LD) function is usually mul­tiplexed onto the LD_SDO
pin. It is suggested that LD only be considered valid when SEN is low. In fact LD will not toggle until
the first active data bit toggles on LD_SDO, and will be restored immediately after the trailing edge
of the LSB of serial data out as shown in Figure 37.
b. The slave (PLL) reads SDI on the 1st rising edge of SCLK after SEN. SDI high ini­tiates the READ
cycle (RD)
c. Host places the six address bits on the next six falling edges of SCLK, MSB first.
d. Slave registers the address bits on the next six rising edges of SCLK (2-7).
e. Slave switches from Lock Detect and places the requested 24 data bits on SD_LDO on the next 24
rising edges of SCK (8-31), MSB first .
f. Host registers the data bits on the next 24 falling edges of SCK (8-31).
g. Slave restores Lock Detect on the 32nd rising edge of SCK.
h. SEN is de-asserted on the 32nd falling edge of SCLK.
i. The 32nd falling edge of SCLK completes the READ cycle.
Table 10. SPI HMC Mode - Read Timing Characteristics
Parameter
Conditions
Min.
t1
SEN to SCLK setup time
8
t2
SDI setup to SCLK time
3
t3
SCLK to SDI hold time
3
t4
SEN low duration
20
t5
SCLK to SDO delay
Typ.
Max.
8.2ns+0.2ns/pF
Units
ns
ns
ns
ns
ns
SCLK
SDI
x
SEN
LD_SDO
2
3
4
5
6
7
8
28
29
30
31
32
t₃
t₂
RD
a5
a4
a3
a2
a1
ao
x
t₁
LD (Lock Detect)
t₅
t₄
d23 d22 d3
d2
d1
d0
LD
Figure 37. HMC Mode Serial Port Timing Diagram - READ
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