HMC704LP4E Datasheet, PDF (36/44 Pages) Hittite Microwave Corporation – 8 GHz fractionaL-N PLL

v04.0215
HMC704LP4E
8 GHZ FRACTIONAL-N PLL
AUX SERIAL PORT
The PLL also features a general purpose 16 bit Aux Serial Port (AuxSPI). The auxiliary serial port may be used to con-
trol other chips if available, via the Open mode protocol.
The AuxSPI outputs the contents of “Reg 05h” upon receipt of a frequency change command. The AuxSPI­data is out-
put at the AuxSPI clock rate which is fpd (“Reg 05h”[6]). A single AuxSPI transfer requires 16 Aux­SPI cycles plus
4 overhead cycles.
REGISTER MAP
Table 13. Reg 00h ID Register (Read Only)
BIT
TYPE
NAME
W DEFLT
[23:0]
RO
chip_ID
24 A7975h
DESCRIPTION
PLL Subsystem ID, 94075
Table 13. Reg 00h Open Mode and HMC Mode Reset Strobe Register (Write Only)
(Continued)
BIT
TYPE
NAME
W DEFLT
DESCRIPTION
[5]
WO
rst_swrst
1
-
Strobe (WRITE ONLY) generates soft reset. Resets all digital and
registers to default states
Table 13. Reg 00h Open Mode Read Address Register (Write Only) (Continued)
BIT
TYPE
NAME
W DEFLT
DESCRIPTION
[4:0]
WO
Open Mode Read Address
5
-
Specifies address to read when in Open Mode 2 cycle read
Table 14. Reg 01h POWERDN Register
BIT
TYPE
NAME
W
[0]
R/W
chipen_pin_select
1
[1]
R/W
chipen_from_spi
1
[2]
R/W
Keep_Bias On
1
[3]
R/W
Keep_PFD_on
1
[4]
R/W
Keep_CP_On
1
[5]
R/W
Keep_Ref_buf ON
1
[6]
R/W
Keep_VCO_on
1
[7]
R/W
Keep_GPO_driver ON
1
[8]
R/W
reserved
1
DEFLT
0
1
0
0
0
0
0
0
0
DESCRIPTION
1 = chip enable via CEN pin, Reg01[0]=1 and CEN pin low puts
PLL in Power Down Mode, see Power Down Mode description
0 = PLL Subsystem chip enable via SPI (rst_chipen_from_spi)
Reg01[1]
Controls PLL Subsystem Chip Enable (Power Down) if rst_chipen_
pin_select
Reg01[0]=0 and Reg01[1]=1 = chip enabled, CEN don’t care
Reg01[0]=0 and Reg01[1]=0 = chip disabled, CEN don’t care
see Power Down Mode description and csp_enable
Keeps internal bias generators on, ignores Chip enable con­trol
Keeps PFD circuit on, ignores Chip enable control
Keeps Charge Pump on, ignores Chip enable control
Keeps Reference buffer block on, ignores Chip enable con­trol
Keeps VCO divider buffer on, ignores Chip enable control
Keeps GPO output Driver ON, ignores Chip enable control
Reserved
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