HMC704LP4E Datasheet, PDF (27/44 Pages) Hittite Microwave Corporation – 8 GHz fractionaL-N PLL

v04.0215
HMC704LP4E
8 GHZ FRACTIONAL-N PLL
Similarly the 24 bit binary value of the fractional word is written into dsm_frac,
1d = 000 001h = 0000 0000 0000 0000 0000 0001
Example 2: Set the output to 7.650 025 GHz using a 100MHz reference, R=2.
Here, output is greater than 4GHz, so we enable the internal divide by 2, d = 1. Find the nearest integer value N_int. N_int =
76, 2f_int = 7.600 000GHz
This leaves the fractional part to be 2f_frac =50.025MHz
= N_frac ²= ²⁴₂^â‹_d^Rf_xt^â‹_al^{ffrac 224 â‹}_{22⋅⋅15000.}= ⁰_×^2150×₆ ¹⁰⁶ 8392802.3
(EQ 8)
Since N_frac must be an integer number, we round it to 8,392,802, and the actual VCO frequency will be 7,650,024,998.19
Hz, an error of -1.81Hz or about 2 parts in 2-10.
Here we program the 16 bit N_int = “Reg 04h”= 76d = 4Ch = 0000 0000 0100 1100 and the 24 bit N_frac = 8,392,802d =
801062h = 1000 0000 0001 0000 0110 0010
In addition to the above frequency programming words, the fractional mode must be enabled using the frac register.
Other DSM configuration registers should be set to the recommended values supplied with the product evaluation
board or available from applications support.
Exact Frequency Mode
The absolute frequency precision of a fractional frequency PLLs is normally limited by the number of bits in the frac-
tional modulator. For example a 24 bit fractional modulator has frequency resolution set by the phase detector (PD )
comparison rate divided by 2²⁴. In the case of a 50MHz PD rate, this would be approximately 2.98 Hz, or 0.0596 ppm.
In some applications it is necessary to have exact frequency steps, and even an error of 3Hz cannot be tol­erated.
In some fractional PLLs it is necessary to shorten the length of the accumulator (the denominator or the modulus) to
accommodate the exact period of the step size. The shortened accumula­tor often leads to very high spurious levels
at multiples of the channel spacing, f_step = f_PD/Modulus. For example 200kHz channel steps with a 10MHz PD rate
requires a modulus of just 50. The HMC method achieves the exact frequency step size while using the full 24 bit modu-
lus, thus achiev­ing exact frequency steps with very low spurious and a high comparison rate, which maintains excellent
phase noise.
Exact frequency steps can be achieved only when the PD rate and the desired frequency step size are related by an
integer multiple. More precisely, the greatest common divisor, (GCD) of the PD rate and the desired frequency step size
must be an integer, and that integer must be less than 2¹⁴-1 or 16,383.
As an example suppose that we want to achieve:
a. Exact channel step size of f_step= 100kHz.
b. Reference Crystal f_xtal = 61.44MHz
c. Phase Detector (PD) Rate f_pd =61.44MHz
d. Channel 1 Frequency, f_vco(CH1) = 2000.200 MHz
Proceed as follows:
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