HMC704LP4E Datasheet, PDF (23/44 Pages) Hittite Microwave Corporation – 8 GHz fractionaL-N PLL

v04.0215
HMC704LP4E
8 GHZ FRACTIONAL-N PLL
5 - 23
Lock Detect Operation with Phase Offset
When operating in fractional mode the linearity of the charge pump and phase detector are much more crit­ical than in
integer mode. The phase detector linearity degrades when operated with zero phase offset. Hence in fractional mode it
is necessary to offset the phase of the reference and VCO at the phase detector. In such a case, for example with an
offset delay, as shown in Figure 32, the VCO arrival may always occur after the reference. The lock detect circuit win-
dow may need to be adjusted to allow for the delay being used, if the delay is large.
LOCK
DETECT
WINDOW
Twindow ~ +10nsec
AVG PHASE OFFSET
VCO AT PD with FRAC Jitter
LOCK WINDOW
AVG PHASE OFFSET
REFERENCE
SIGNAL
REF PHASE ARRIVAL
AVG VCO PHASE OFFSET
FRACTIONAL MODE
REF PHASE ARRIVAL
VCO ARRIVAL DISTRIBUTION AT PD
AVG VCO PHASE OFFSET
FRACTIONAL MODE
Figure 32. Lock Detect Window - Fractional Mode with Offset
PHASE JITTER
AT PD
In integer mode, 0 offset is recommended. In fractional mode, the time offset should be set to ~ 2.5 ns + 4 Tps, where
Tps is the RF period at the fractional prescaler input (i.e. after the optional fixed divide by 2). Refer to the Fractional
Operation section for further details about calculating charge pump offset currents
Digital Lock Detect with Digital Window Example
Typical Digital Lock detect window widths are shown in Table 7. Lock Detect windows typically vary +/-10% vs voltage
and +/-15% over -40 C to +85 C.
Table 7. Typical Digital Lock Detect Window
LD Timer Speed
Reg07[11:10]
Digital Lock Detect Window
Nominal Value +/-25%
(nsec)
Fastest 00 6.5
8.0 11.0
17
29
53
01 7.0
8.9
12.8
21
36
68
10 7.1
9.2
13.3
22
38
72
Slowest 11 7.6
10.2 15.4
26
47
88
LD Timer Divider Setting
Reg07[9:7]
0
1
2
3
4
5
LD Timer Divider Value
0.5
1
2
4
8
16
100 195
130 255
138 272
172 338
6
7
32
64
As an example, if we operate in fractional mode at 2.7 GHz with a 50 MHz PD, charge pump gain of 2 mA and a down
leakage of 400 uA. Then our average offset at the PD will be 0.4 mA/2 mA = 0.2 of the PD period or about 4 ns (0.2 x
1/50 MHz). However, the fractional modulation of the VCO divider will result in time excursions of the VCO divider output
of +/-4Tvco (assuming the internal 8 GHz Divide-by-2 is not enabled. See Reg 8 Bit [19]) from this average value
(+/-1.5ns in this example). Hence when in lock, the divided VCO will arrive at the PD about 4 +/-1.5 ns after the divided
reference. The Lock Detect window always starts on the arrival of the first signal at the PD, in this case the reference.
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