HMC704LP4E Datasheet, PDF (39/44 Pages) Hittite Microwave Corporation – 8 GHz fractionaL-N PLL

v04.0215
HMC704LP4E
8 GHZ FRACTIONAL-N PLL
Table 20. Reg 07h Lock Detect Register
BIT
TYPE
NAME
W DEFLT
[2:0]
R/W
lkd_wincnt_max
3
5
[3]
R/W
Enable Internal Lock Detect
1
1
[5:4]
R/W
Reserved
2
0
[6]
R/W
Lock Detect Window type
1
0
[9:7]
R/W
LD Digital Window duration
3
0
[11:10]
R/W
LD Digital Timer Freq Con­trol
2
0
[12]
R/W
LD Timer Test Mode
1
0
[13]
R/W
Auto Relock - One Try
1
0
DESCRIPTION
Lock Detect window sets the number of consecutive counts of
divided VCO that must land inside the Lock Detect Window to
declare LOCK
0: 5
1: 32
2: 96
3: 256
4: 512
5: 2048
6: 8192
7: 65535
Enable Internal Lock Detect
Reserved
Lock Detection Window Timer Selection
1: Digital programmable timer
0: Analog one shot, nominal +/-10nsec window
Lock Detection - Digital Window Duration
0: 1/2 cycle
1: 1 cycle
2: 2 cycles
3: 4 cycles
4: 8 cycles
5: 16 cycles
6: 32 cycles
7: 64 cycles
Lock Detect Digital Timer Frequency Control
“00” fastest “11” slowest
1: Force Timer ON Continuously - For Test Only
0: Normal Timer operation - one shot
1: Attempts to relock if Lock Detect fails for any reason
Only tries once.
Table 21. Reg 08h Analog EN Register
BIT
TYPE
NAME
W
0
R/W
bias_en
1
1
R/W
cp_en
1
2
R/W
pd_en
1
3
R/W
refbuf_en
4
R/W
vcobuf_en
1
5
R/W
GPO/LDO/SDO_pad_en
1
6
R/W
Reserved
1
7
R/W
VCO_Div_Clk_to_dig_en
1
8
R/W
Reserved
1
DEFLT
1
1
1
1
1
1
1
1
0
DESCRIPTION
Enables main chip bias reference. Program 1b
Charge pump enable Program 1b
PD enable Program 1b
Reference path buffer enable Program 1b
VCO path RF buffer enable Program 1b
0 - Pin LD_SDO disabled
1 - and Reg0Fh[7]=1, Pin LD_SDO is always on (required to output
LD state or view GPO signals).
1 - and Reg0Fh[7]=0, Pin LD_SDO only outputs SDO data provided
Reg0Fh[6]=0.
Program 1b
VCO Divider Clock to Digital Enable Program 1b
Program 0
5 - 39
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