HMC704LP4E Datasheet, PDF (24/44 Pages) Hittite Microwave Corporation – 8 GHz fractionaL-N PLL

v04.0215
HMC704LP4E
8 GHZ FRACTIONAL-N PLL
The Lock Detect window must be longer than 4 ns + 1.5 ns (5.5 ns) and shorter than the period of the PD, in this exam-
p
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e
,
20 ns. A perfect Lock Detect window would be midway between these two values, or 12.75 ns.
Tolerance on the window is +25% at +85 C, -25% at -40 C. Here 12.8 ns nominal window may extend by +25% at +85C
to 16 ns, which is fine for a PD period of 20 ns. Also the minimum window may shrink by 25% to 9.6ns at -40C, which
again works well for the DC offset of 5.5 ns.
PD Period 20ns
Ref at PD
VCO at PD
VCO Offset 4ns
-Window Margin
LD WINDOW
LD Window 12.8 ns+/-25%
+Window Margin
Figure 33. Lock Detect Window Example with 50MHz PD and 4ns VCO Offset
There is always a good solution for the lock detect window for a given operating point. The user should understand
however that one solution does not fit all operating points. If charge pump offset or PD fre­quency are changed signifi-
cantly then the lock detect window may need to be adjusted.
Cycle Slip Prevention (CSP)
When changing frequency and the VCO is not yet locked to the reference, the instantaneous frequencies of the two PD
inputs are different, and the phase difference of the two inputs at the PD varies rapidly over a range much greater than
+/-2π radians. Since the gain of the PD varies linearly with phase up to +/-2π, the gain of a conventional PD will cycle
from high gain, when the phase difference approaches a multiple of 2π, to low gain, when the phase difference is
slightly larger than 0 radians. The output current from the charge pump will cycle from maximum to minimum even
though the VCO has not yet reached its final frequency.
The charge on the loop filter small cap may actually discharge slightly during the low gain portion of the cycle. This can
make the VCO frequency actually reverse temporarily during locking. This phenomenon is known as cycle slipping.
Cycle slipping causes the pull-in rate during the locking phase to vary cyclically. Cycle Slipping increases the time to
lock to a value much greater than that predicted by normal small signal Laplace analysis.
The PLL PD features an ability to reduce cycle slipping during acquisition. The Cycle Slip Preven­tion (CSP) feature in-
creases the PD gain during large phase errors. The specific phase error that triggers the momentary increase in PD
gain is set via “Reg 0Bh”[8:7].
PD Polarity
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