HMC704LP4E Datasheet, PDF (35/44 Pages) Hittite Microwave Corporation – 8 GHz fractionaL-N PLL

v04.0215
HMC704LP4E
8 GHZ FRACTIONAL-N PLL
SCLK
SDI
LD_SDO
t₁
t₂
FIRST CYCLE
2
19
20
21
24
25
26
29
30
31
32
x
d5
d4
d0
r4
r0
a2
a1
a0
x
t₅
LD
x
x
READ Address
Register Address = 00000
Chip Address = 000
x
x
x
x
x
x
x
x
x
LD
SEN
SCLK
SDI
t₆
t₄
SECOND CYCLE
2
19
20
21
24
25
26
30
31
32
x
d23
d5
d4
d0
r4
r0
a2
a1
a0
x
LD_SDO
LD
d31 d30
d10
d9
d8
d7
d6
d3
d2
d1
d0
LD**
SEN
t₃
**Note: Read-back on LD_SDO can function without SEN, however SEN
rising edge is required to return the LD_SDO to the LD state
Figure 39.Open Mode - Serial Port Timing Diagram - READ Operation 2-Cycles
5 - 35
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Trademarks and registered tradem_Aark_ps_par_le_icth_ae _tp_ir_oop_nert_sy _uof_pth_peir_ore_rs_tp_:e_Pcti_hve_oo_nw_ene_:rs₉. _{78-250-3343 o}A_rpp_Rli_Fca_Mtio_Gn _-S_au_pp_ppo_sr_@t: _aPh_no_an_le_o:_g1_.-_c8_o00_m-ANALOG-D