HMC704LP4E Datasheet, PDF (42/44 Pages) Hittite Microwave Corporation – 8 GHz fractionaL-N PLL

v04.0215
HMC704LP4E
8 GHZ FRACTIONAL-N PLL
Table 24. Reg 0Bh PD Register
BIT
TYPE
NAME
[2:0]
R/W
pd_del_sel
[3]
R/W
Short PD Inputs
[4]
R/W
pd_Invert
[5]
R/W
[6]
R/W
pd_up_en
pd_dn_en
[8:7]
R/W
CSP Mode
[9]
R/W
[10]
R/W
[11]
R/W
Force CP UP
Force CP DN
Force CP MId Rail
[14:12]
R/W
PS Bias
[16:15]
R/W
CP Internal OpAmp Bias
[18:17]
R/W
MCounter Clock Gating
[19]
[21:20]
[23:22]
R/W
R/W
R/W
Spare
Divider Pulse Width
Reserved
W DEFLT
DESCRIPTION
3
1
Sets PD reset path delay
1
0
Shorts the inputs to the Phase Detector - Test Only
Inverts the PD polarity
0 - Use with a positive tuning slope VCO and passive loop filter
1
0
(default).
1 - Use with a negative slope VCO or with an inverting active loop
filter with a positive slope VCO.
1
1
Enables the PD UP output, see also Reg0B[9]
1
1
enables the PD DN output, see also Reg0B[9]
Cycle Slip Prevention Mode
Extra current (~8mA) is driven into the loop filter when the phase
error is larger than:
0: CSP Disabled
1: CP Gain increased if Phase Error > 6 nsec
2
0
2: CP Gain increased if Phase Error > 14 nsec
3: CP Gain increased if Phase Error > 24 nsec
This phase error delay varies +/-10% with temperature and +/-12%
with process.
CSP should only be used with comparison frequencies < = 50 MHz
and disabled otherwise. Always confirm loop stability when using
CSP
1
0
Forces CP UP output on - Use for Test only
1
0
Forces CP DN output on - Use for Test only
1
0
Force CP MId Rail - Use for Test only
Prescaler Bias
0: Nominal
3
0
1: +20% RF Buffer
2: +25% Rsync
3: +50%
2
3
CP Internal OpAmp Bias
MCounter Clock Gating
0: MCounter Off for N < 32
2
3
1: N<128
2: N< 1023
3: All Clocks ON
1
1
Don’t care
2
0
0: shortest, ... 3: Longest
2
0
Irrliniecgfseohpntrsomsenoa_{Fsftiisibtoohingilrrirtdyafupnpirstnaerairdi}sts_{cihesbeseuydmt,himebaddtyp9melbiAc7yalanyi8Ataviorln-}oe_ena2gsl_{ruoo5ylDrgt 0}eofDr_avtoh_-eimcnev3eri_dcwi3stesis_4siutse_{ofs3obeur.nepitdtSle}isee_lpavur_{leescac•}deinf,_eiyctn9oaop_7otriaboft8renoe_dsrn-ata_{2escnouc5ryrbusjip0ern:}aacf_{-rttteiAe3ntnoga3ntecnrma7hdigae3lhnrontegstlgfseiaoaobwffDx}lAiepthn.a_{e•oatHuelvotoOngi}wnt_csorDeeotdviecre_{sveeori,.c,threNneIsooonr. ncl.FOPi,nohnOeroennpTaereeti:cc7wTeh8,en1wodc-3lewho2lgin.9vayeo-4nrWly7oa,a0glya0o,yng•PdW..OOctora.odBymep,orlax/Nohcn9eoil1tirnt0oiwe6trde,aoeNmtorwosdw:rww,AwoMno.aadAlno,agM0lo2ADg0e.0cv62oic02me6s2,-9In10c.6,}
Trademarks and registered tradem_Aar_pks_par_le_icth_ae_tp_ir_oop_ner_sty_uof_pth_pei_or r_re_ts_:pe_Pct_hive_oo_nw_ene_:rs₉. _{78-250-3343 o}A_rpp_Rli_Fca_Mtio_Gn_-S_au_pp_pp_sor_@t:_aP_nho_an_loe:_g1_.-_c8_o0_m0-ANALOG-D
5 - 42