HMC704LP4E Datasheet, PDF (33/44 Pages) Hittite Microwave Corporation – 8 GHz fractionaL-N PLL

v04.0215
HMC704LP4E
8 GHZ FRACTIONAL-N PLL
Open Mode - Serial Port WRITE Operation
AVDD = DVDD = 3.3V +/-10%, AGND = DGND = 0V
Table 11. SPI Open Mode - Write Timing Characteristics
Parameter
Conditions
Min.
Typ.
Max.
Units
t1
SDI setup time
t2
SDI hold time
t3
SEN low duration
t4
SEN high duration
t5
SCLK 32 Rising Edge to SEN Rising Edge
Serial port Clock Speed
3
1
10
10
10
DC
50
ns
ns
ns
ns
ns
MHz
A typical WRITE cycle is shown in Figure 38.
a. The Master (host) places 24 bit data, d23:d0, MSB first, on SDI on the first 24 falling edges of SCLK.
b. the slave (PLL) shifts in data on SDI on the first 24 rising edges of SCLK
c. Master places 5 bit register address to be written to, r4:r0, MSB first, on the next 5 falling edges of
SCLK (25-29)
d. Slave shifts the register bits on the next 5 rising edges of SCLK (25-29).
e. Master places 3 bit chip address, a2:a0, MSB first, on the next 3 falling edges of SCLK (30-32).
Hittite reserves chip address a2:a0 = 000 for all RF PLL-VCOs.
f. Slave shifts the chip address bits on the next 3 rising edges of SCLK (30-32).
g. Master asserts SEN after the 32nd rising edge of SCLK.
h. Slave registers the SDI data on the rising edge of SEN.
i. Master clears SEN to complete the WRITE cycle.
SCLK
SDI
t₁
2
3
t₂
22
23
24
25
26
t₅
31
32
x
d22
d2
d1
d0
r4
r3
r0
a2
a1
a0
x
SEN
t₄
t₃
Figure 38. Open Mode - Serial Port Timing Diagram - WRITE
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