HMC704LP4E Datasheet, PDF (21/44 Pages) Hittite Microwave Corporation – 8 GHz fractionaL-N PLL

v04.0215
HMC704LP4E
8 GHZ FRACTIONAL-N PLL
φ ²( ^f)
^{r2 ⁄ Hz}
φ² ( ^f _o)
f_o
B
фrms
ф(t)
Figure 30. Synthesizer Phase Noise and Jitter
With this simplification the total integrated VCO phase noise, Φ_ν² , in rads² is given by
Φ_ν² =Φ² ₍ f_{0 )} Bπ
(EQ 5)
where
Φ² (f₀ ) _{is the single sideband phase noise in rads}2_{/Hz inside the loop bandwidth, and}
B is the 3dB corner frequency of the closed loop PLL
The
integrated
phase
noise
at
the
phase
detector,
Φ
2
pd
,
is
just
scaled
by
N²
ie.
Φ²_pd =Φ_N^ν₂₂
The rms phase jitter of the VCO ( Φ_v) in rads, is just the square root of the phase noise integral.
Since the simple integral of (EQ 5) is just a product of constants, we can easily do the integral in the log domain. For
example if the phase noise inside the loop is -110 dBc/Hz at 10 kHz offset and the loop band­width is 100 kHz, and the
division ratio is 100, then the integrated phase noise at the phase detector, in dB, is given by;
( ) ^−95
Φ= ²_pddB 10log Φ² (f₀ )βπ N² = -110 + 5 +50 - 40 = -95 dBrads, or equivalently Φ =10 ²⁰ = 18urads = 1 milli-degrees
rms.
While the phase noise reduces by a factor of 20logN after division to the reference, due to the increased period of the
PD reference signal, the jitter is constant.
The rms jitter from the phase noise is then given by T_jp=_n T_pdΦ _pd 2π
In this example if the PD reference was 50 MHz, T_pd = 20 nsec, and hence T_jpn = 56 femto-sec.
PD Window Based Lock Detect
Lock Detect Enable “Reg 07h”[3] = 1 is a global enable for all lock detect functions.
The window based Lock Detect circuit effectively measures the difference between the arrival of the refer­ence and the
divided VCO signals at the PD. The arrival time difference must consistently be less than the Lock Detect window
length, to declare lock. Either signal may arrive first, only the difference in arrival times is counted.
5 - 21
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