HMC704LP4E Datasheet, PDF (20/44 Pages) Hittite Microwave Corporation – 8 GHz fractionaL-N PLL

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HMC704LP4E
8 GHZ FRACTIONAL-N PLL
RF Path ’N’ Divider
The main RF path ’N’ divider is capable of divide ratios anywhere between 2¹⁹-1 (524,287) and 16 . This divider for ex-
ample could divide a 4 GHz input to a PD frequency anywhere between its maximum output limit of 115 MHz to as low
as 7.6 kHz. The ’N’ divider output may be viewed in test mode on LD_SDO by set­ting “Reg 0Fh”[4:0] = 10 d. When oper-
ating in fractional mode the N divider can change by up to +/-4 from the average value. Hence the selected divide ratio
in fractional mode is restricted to values between 2¹⁹-5 (524,283) and 20.
If the VCO input is above 4 GHz then the 8 GHz fixed RF divide-by-2 should be used, “Reg 08h”[19] = 1. In this case the
total division range is restricted to even numbers over the range 2*(2¹⁹-5) (1,048,566) to 40.
Charge Pump and Phase Detector
The Phase Detector or PD has two inputs, one from the reference path divider and one from the RF path divider. When
in lock these two inputs are at the same average frequency and are fixed at a constant aver­age phase offset with re-
spect to each other. We refer to the frequency of operation of the PD as f_pd. Most formula related to step size, delta-sig-
ma modulation, timers etc., are functions of the operating frequency of the PD, f_pd is sometimes referred to as the com-
parison frequency of the PD.
The PD compares the phase of the RF path signal with that of the reference path signal and controls the charge pump
output current as a linear function of the phase difference between the two signals. The out­put current varies in a linear
fashion over nearly ±2π radians (±360) of input phase difference.
Phase Detector and Charge Pump Functions
Phase detector register “Reg 08h” allows manual access to control special phase detector features.
“Reg 0Bh”[2:0] allows fine tuning of the PD reset path delay. This adjustment can be used to improve perfor­mance at
very high PD rates. Most often this register is set to the recommended value only.
“Reg 06h”[5] and [6] enables the PD UP and DN outputs respectively. Disabling prevents the charge pump from pump-
ing up or down respectively and effectively tri-states the charge pump while leaving all other functions operating inter-
nally.
CP Force UP “Reg 08h”[9] and CP Force DN “Reg 00h”[10] allows the charge pump to be forced up or down respec-
tively. This will force the VCO to the ends of the tuning range which can be useful for testing of the VCO.
PD Force Mid “Reg 0Bh”[11] will disable the charge pump current sources and place a voltage source on the loop filter
at approximately VPPCP/2. If a passive filter is used this will set the VCO to the mid-voltage tun­ing point which can be
useful for testing of the VCO.
“Reg 0Bh”[21:7] control other aspects of the phase detector operation and should be set to recommended values.
PLL Jitter
The standard deviation of the arrival time of the VCO signal, or the jitter, may be estimated with a simple approximation
if we assume that the locked VCO has a constant phase noise, Φ² (f₀ ) , at offsets less than the loop 3 dB bandwidth and
a 20 dB per decade roll off at greater offsets. The simple locked VCO phase noise approximation is shown on the left of
Figure 30.
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