HMC704LP4E Datasheet, PDF (30/44 Pages) Hittite Microwave Corporation – 8 GHz fractionaL-N PLL

v04.0215
HMC704LP4E
8 GHZ FRACTIONAL-N PLL
Register 0 Modes
Register 0 has a dedicated function in each mode. Open Mode allows wider compatibility with other manu­facturers SPI
protocols.
Table 8. Register 0 Comparison - Single vs Multi-User Modes
Single User
HMC Mode
Single Or Multi-User
Open Mode
READ
Chip ID
24 Bits
Chip ID
24 Bits
WRITE
Soft Reset,
General Strobes
Read Address [4:0]
Soft reset [5]
General Strobes [24:6]
Serial Port Mode Decision after Power-On Reset
On power up, both types of modes are active and listening. All digital IO must be low at power-up.
A decision to select the desired Serial Port mode (protocol) is made on the first occurrence of SEN or SCLK, after which
the Serial Port mode is fixed and only changeable by a power down.
a. If a rising edge on SEN is detected first HMC Mode is selected.
b. If a rising edge on SCLK is detected first Open mode is selected.
Serial Port HMC Mode - Single PLL
HMC Mode (Legacy Mode) serial port operation can only address and communicate with a single PLL, and is compat­
ible with most HMC PLLs and PLLs with integrated VCOs.
The HMC Mode protocol for the serial port is designed for a 4 wire interface with a fixed protocol featuring
a. 1 Read/Write bit
b. 6 Address bits
c. 24 data bits
Serial Port Open Mode
The Serial Port Open Mode features:
a. Compatibility with general serial port protocols that use a shift and strobe approach to com­
munication.
b. Compatible with HMC multi-Chip solutions, useful to address multiple chips of various types from a
single serial port bus.
The HMC Open Mode protocol has the following general features:
a. 3 bit chip address, can address up to 8 devices connected to the serial bus
b. Wide compatibility with multiple protocols from multiple vendors
c. Simultaneous Write/Read during the SPI cycle
d. 5 bit register address space
e. 3 wire for Write Only capability, 4 wire for Read/Write capability.
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