Z8523016VEG Datasheet, PDF (90/118 Pages) Zilog, Inc. – Enhanced Serial Communications Controller

Z80230/Z85230/L
Product Specification
85
Table 45. Z80230 AC Characteristics (Continued)
10 MHz
16 MHz
No Symbol
Parameter
Min. Max.
Min. Max
Notes
34 TdIEI (IEO) IEI to IEO Delay
90
45
8
35 TdAS (IEO) AS Rise to IEO Delay
175
80
6
36 TdDSA (INT) DS Fall (Acknowledge) to INT
450
Inactive Delay
200
4, 8
37 TdDS (ASQ) DS Rise to AS Fall Delay for No 15
10
8
Reset
38 TdASQ (DS) AS Rise to DS Fall Delay for No 15
10
8
Reset
39 TwRES
AS and DS Coincident Low for 100
75
8
Reset7
40 TwPCl
PCLK Low Width
40
100
26
1000 8
41 TwPCh
PCLK High Width
40
1000 26
1000
8
42 TcPc
PCLK Cycle Time
100
2000
61
2000 8
43 TrPC
PCLK Rise Time
10
5
8
44 TfPC
PCLK Fall Time
10
5
8
Notes:
1. Parameter does not apply to Interrupt Acknowledge transactions.
2. Parameter applies only between transactions involving the ESCC.
3. Float delay is defined as the time required for a ±0.5 V change in the output with a maximum DC load and a min-
imum AC load.
4. Open-drain output, measured with open-drain test load.
5. Parameter is system-dependent. For any Zilog ESCC in the daisy chain. TdAS (DSA) must be greater than the
sum of TdAS (IEO) for the highest priority device in the daisy chain. TsIEI (DSA) for the Zilog ESCC, and TdIEI
(IEO) for each device separating them in the daisy chain.
6. Parameter applies only to a Zilog ESCC pulling INT Low at the beginning of the Interrupt Acknowledge transac-
tion.
7. Internal circuitry allows for the reset provided by the Z8^® to be recognized as a reset by the Z-ESCC. All timing
references assume 2.0 V for a 1 and 0.8 V for a logic 0.
8. Units in ns.
9. Units inTcPc
PS005308-0609
Electrical Characteristics