Z8523016VEG Datasheet, PDF (25/118 Pages) Zilog, Inc. – Enhanced Serial Communications Controller

Z80230/Z85230/L
Product Specification
20
For FM encoding, the DPLL counts from 0 to 32, but with a cycle corresponding to two
bit times. When the DPLL is locked, the clock edges in the data stream occurs between
counts 15 and 16 and between counts 31 and 0. The DPLL looks for edges only during a
time centered on the 15 to 16 counting transition.
The 32x clock for the DPLL can be programmed to come from either the RTxC input or
the output of the BRG. The DPLL output is programmed to be echoed out the ESCC by the
TRxC pin (if this pin is not being used as an input).
Data Encoding
Data encoding allows the transmission of clock and data information over the same
medium. This capability saves the need to transmit clock and data over separate medium
as is normally required tor synchronous data. The ESCC provides four different data
encoding methods, selected by bits 6 and 5 in WR10. Examples of these 4 encoding meth-
ods is displayed in Figure 11. Any encoding method is used in any X1 mode in the ESCC,
ASYNCHRONOUS or SYNCHRONOUS. The data encoding selected is active even if
the transmitter or receiver is idling or disabled.
1
1
0
0
1
0
Data
NRZ
NRZI
FM1
FM0
Figure 11. Data Encoding Methods
Table 3 lists the four encoding methods, their levels, and values.
Table 3. Data Encoding Descriptions
Code Type
NRZ
NRZI
Level
High
Low
No Change
Change
Value
1
0
1
0
PS005308-0609
Functional Description