Z8523016VEG Datasheet, PDF (17/118 Pages) Zilog, Inc. – Enhanced Serial Communications Controller

Z80230/Z85230/L
Product Specification
12
Pending register. Status information for both channels resides in one register. Only one
register may be read. Depending on its contents, the CPU performs one of the three opera-
tions listed below:
1. Write data
2. Read data
3. Continues processing
Two bits in the register indicate the requirement for data transfer.
INTERRUPT
The ESCC INTERRUPT mode supports vectored and nested interrupts. The fill levels at
which the transmit and receive FIFOs interrupt the CPU are programmable, allowing the
ESCC requests for data transfer to be tuned to the system interrupt response time.
Nested interrupts are supported with the interrupt acknowledge (INTACK) feature of the
ESCC. It allows the CPU to acknowledge the occurrence of an interrupt, and re-enable
higher priority interrupts. Since an INTACK cycle releases the INT pin from the active
state, a higher priority ESCC interrupt or another higher priority device can interrupt the
CPU. When an ESCC responds to INTACK signal from the CPU, it can place an interrupt
vector on the data bus. This vector is written in WR2 and may be read in RR2. To increase
the interrupt response time, the ESCC can modify 3 bits in this vector to indicate status. If
the vector is read in Channel A, status is not included. If it is read in Channel B, status is
included.
Each of the six sources of interrupts in the ESCC (Transmit, Receive, and External/Status
interrupts in both channels) has 3 bits associated with the interrupt source as listed below:
1. Interrupt Pending (IP)
2. Interrupt Under Service (IUS)
3. Interrupt Enable (IE)
If the IE bit is set for a given interrupt source, then that source can request interrupts.
However, when the Master Interrupt Enable (MIE) bit in WR9 is reset, no interrupts can
be requested. The IE bits are write-only. The other two bits are related to the interrupt pri-
ority chain (see Figure 7 on page 13). The ESCC can request an interrupt only when no
higher priority device is requesting an interrupt (that is, when IEI is High). If the device in
question requests an interrupt, it pulls down INT. The CPU then responds with INTACK,
and the interrupting device places a vector on the data bus.
PS005308-0609
Functional Description