Z8523016VEG Datasheet, PDF (15/118 Pages) Zilog, Inc. – Enhanced Serial Communications Controller

Z80230/Z85230/L
Product Specification
10
Note:
Throughout this document the Write and Read registers are referenced with the notations
WR for Write Register and RR for Read Register. For example:
WR4A – Write Register 4 for Channel A
RR3 – Read Register 3 for either or both channels
Table 1. ESCC Write Registers
Write Register
WR0
WR1
WR2
WR3
WR4
WR5
WR6
WR7
WR7’
WR8
WR9
WR10
WR11
WR12
WR13
WR14
WR15
Functions
Command Register; Select Shift Left/Right Mode, Cyclic
Redundancy Check (CRC) Initialization, and Resets for
Various Modes
Interrupt Conditions, Wait/DMA Request Control
Interrupt Vector, Accessed Through Either Channel
Receive and Miscellaneous Control Parameters
Transmit and Receive Parameters and Modes
Transmit Parameters and Controls
SYNC Character or SDLC Address Field
SYNC Character or SDLC Flag
SDLC Enhancements Enable, Accessible if WR15 bit D0 is 1
Transmit FIFO, 4-Bytes Deep
Reset Commands and Master INT Enable, Accessible
Through Either Channel
Miscellaneous Transmit and Receive Controls
Clock Mode Control
Lower Byte of BRG Time Constant
Upper Byte of BRG Time Constant
Miscellaneous Controls and Digital Phase-Locked Loop
(DPLL) Commands
External Interrupt Control
PS005308-0609
Functional Description