Z8523016VEG Datasheet, PDF (27/118 Pages) Zilog, Inc. – Enhanced Serial Communications Controller

Z80230/Z85230/L
Product Specification
22
Z80230/Z85230/L Enhancements
A detailed description of the enhancements to the Z80230/Z85230/L ESCC that differenti-
ate it from the standard SCC is provided below:
4-Byte Transmit FIFO Buffer
The ESCC has a 4-byte transmit buffer with programmable interrupt and DMA request
levels. It is not necessary to enable the FIFO buffer as it is always available. You can set
the Transmit Buffer Empty (TBE) interrupt and DMA Request on Transmit command to
be generated either when the top byte of transmit FIFO is empty or only when the FIFO is
completely empty. A hardware or channel reset clears the transmit shift register, flushes
the transmit FIFO, and sets WR7’ bit 5 to 1.
If the transmitter generates the interrupt or DMA request for data when the top byte of the
FIFO is empty (WR7’ bit 5 is 0), the system allows for a long response time to the data
request without underflowing. The interrupt service routine (ISR) writes 1byte and then
tests RR0 bit 2. The DMA Request on Transmit in this mode is set to 0 after each data
Write (that is, TBE), RR0 bit 2, is set to 1 when the top byte of the FIFO is empty. WR7’
bit 5 resets to 1.
In applications for which the interrupt frequency is important, the transmit ISR can be
optimized by programming the ESCC to generate the TBE interrupt only when the FIFO is
completely empty (WR7’ bit 5 is 1) and, writing 4 bytes to fill the FIFO. When WR7’ bit
5 is 1, only one DMA request is generated, filling the bottom of the FIFO. However, this
may be advantageous for applications where the possible reassertion of the DMA request
is not required. The TBE status bit, RR0 bit 2, is set to 1 when the top byte of the FIFO is
empty. WR7’ bit 5 is set to1 after a hardware or channel reset.
8-Byte Receive FIFO
The ESCC has an 8-byte receive FIFO with programmable interrupt levels. It is not neces-
sary to enable the 8-byte FIFO as it is always available. A hardware or channel reset clears
the Receive Shift register and flushes the Receive FIFO. The Receive Character Available
interrupt is generated as selected by WR7’ bit 3. The Receive Character Available bit,
RR0 bit 0 is set to 1 when at least one byte is available at the top of the FIFO (independent
of WR7’ bit 3).
A DMA Request on Receive, if enabled, is generated whenever 1 byte is available in the
receive FIFO independent of WR7’ bit 3. If more than 1 byte is available in the FIFO, the
Wait/Request pin becomes inactive and becomes active when the FIFO is emptied.
PS005308-0609
Z80230/Z85230/L Enhancements