Z8523016VEG Datasheet, PDF (118/118 Pages) Zilog, Inc. – Enhanced Serial Communications Controller

Z80230/Z85230/L
111
S
SDLC
CRC polynomial 17
FIFO frame status enhancement 28
loop mode 18
mode, CRC reception 26
mode, TxD forced high 26
status FIFO 19
status FIFO anti-lock feature 31
transmit data interrupt response 28
SDLC FIFO overflow problem
description 103
solutions 103
SDLC mode 17
software interrupt acknowledge 28
standard test conditions 75
synchronization
external 4
internal 4
synchronous modes 16
system timing characteristics table, Z85230 98
T
timing, Z85230 72
transmit buffer empty interrupt 22
transmit clock counter 5
Tx underrun/EOM interrupt 28
TxD forced high in SDLC mode 26
TxD forced high problem
description 102
solutions 103
TxIP latch 26
V
vector includes status (VIS) 28
VIS 28
W
WR 10
WR7’ 9, 23
write cycle timing
Z80230 70
Z85230 73
write register (WR) 10
write register 7 prime (WR&’) 23
write register 7 prime (WR7’) 9
bit 0 25
bit 1 25
bit 2 25
bit 3 25
bit 4 24
bit 5 24
bit 6 24
bit 7 24
write registers 32
PS005308-0609
PRELIMINARY
Index