Z8523016VEG Datasheet, PDF (11/118 Pages) Zilog, Inc. – Enhanced Serial Communications Controller

Z80230/Z85230/L
Product Specification
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INT (Interrupt (Output, Open-Drain, Active Low))—This pin activates when the ESCC
requests an interrupt. The INT is an open-drain output.
INTACK (Interrupt Acknowledge (Input, Active Low))—This pin is a strobe which indi-
cates that an Interrupt Acknowledge Cycle is in progress. During this cycle, the ESCC
interrupt daisy chain is resolved. The device can return an interrupt vector that may be
encoded with the type of interrupt pending. During the acknowledge cycle, if IEI is High,
the ESCC places the interrupt vector on the data bus when RD goes active for the Z85230/
L, or when DS goes active for the Z80230. INTACK is latched by the rising edge of
PCLK.
Pin Descriptions Exclusive to the Z85230/L
The pin description for pins exclusive to Z85230/L is provided below:
Pins D7–D0 (Data Bus (Bidirectional, tristate))—These pins carry data and commands
to and from the Z85230/L.
CE (Chip Enable (Input, Active Low))—This pin selects the Z85230/L for a Read or
Write operation.
RD ((Read (input, Active Low))—This pin indicates a Read operation and, when the
Z85230/L is selected, enables the Z85230/L’s bus drivers. During the Interrupt Acknowl-
edge cycle, RD gates the interrupt vector onto the bus if the Z85230/L is the highest prior-
ity device requesting an interrupt.
WR (Write (Input, Active Low))—When the Z85230/L is selected, this pin denotes a
Write operation, which indicates that the CPU writes command bytes or data to the
Z85230/L write registers.
Note: WR and RD going Low simultaneously is interpreted as a Reset.
A/B (Channel A/Channel B (Input))—This pin selects the channel in which the Read or
Write operation occurs. A High selects Channel A and a Low selects Channel B.
D/C (Data/Control Select (Input))—This signal defines the type of information trans-
ferred to or from the Z85230/L. A High indicates data transfer and a Low indicates a com-
mand transfer.
Pin Descriptions Exclusive to the Z80230
The pin description for pins exclusive to Z80230 is provided below:
AD7–AD0 (Address/Data Bus (Bidirectional, Active High, tristate))—These multi-
plexed lines carry register addresses to the Z80230 as well as data or control information
to and from the Z80230.
R/W (Read/Write (Input, Read Active High))—This pin specifies if the operation to be
performed is a Read or Write operation.
PS005308-0609
Pin Descriptions