Z8523016VEG Datasheet, PDF (40/118 Pages) Zilog, Inc. – Enhanced Serial Communications Controller

Z80230/Z85230/L
Product Specification
35
Table 6 lists details of the Z80X30 Register Map in SHIFT RIGHT mode.
Table 6. Z80X30 Register Map (Shift Right Mode)
AD4
AD3
AD2
AD1
AD0
Write
80230
80230
80230 WR15 D2=1
WR15 D2=0 WR15 D2=1 WR7’ D6=1
0
0
0
0
0
WR08
RR0B
RR0B
RR0B
0
0
0
0
1
WR0A
RR0A
RR0A
RR0A
0
0
0
1
0
WR1B
RR1B
RR1B
RR1B
0
0
0
1
1
WR1A
RR1A
RR1A
RR1A
0
0
1
0
0
WR2
RR2B
RR2B
RR2B
0
0
1
0
1
WR2
RR2A
RR2A
RR2A
0
0
1
1
0
WR3B
RR3B
RR3B
RR3B
0
0
1
1
1
WR3A
RR3A
RR3A
RR3A
0
1
0
0
0
WR4B
(RR0B)
(RR0B)
(WR4B)
0
1
0
0
1
WR4A
(RR0A)
(RR0A)
(WR4A)
0
1
0
1
0
WR5B
(RR1B)
(RR1B)
(WR5B)
0
1
0
1
1
WR5A
(RR1A)
(RR1A)) (WR5A)
0
1
1
0
0
WR6B
(RR2B)
RR12B
RR12B
0
1
1
0
1
WR6A
(RR2A)
RR13B
RR13B
0
1
1
1
0
WR7B
(RR3B)
RR14B
(WR7’B)
0
1
1
1
1
WR7A
(RR3A)
RR15B
RR15B
1
0
0
0
0
WR8B
RR8B
RR8B
RR8B
1
0
0
0
1
WR8A
RR8A
RR8A
RR8A
1
0
0
1
0
WR9
(RR13B) (RR13B) (WR3B)
1
0
0
1
1
WR9
(RR13A) (RR13A) (WR3A)
1
0
1
0
0
WR10B
RR10B
RR10B
RR10B
1
0
1
0
1
WR10A
RR10A
RR10A
RR10A
1
0
1
1
0
WR11B (RR15B) (RR15B) (WR10B)
1
0
1
1
1
WR11A (RR15A) (RR15A) (WR10A)
1
1
0
0
0
WR12B
RR12B
RR12B
RR12B
1
1
0
0
1
WR12A
RR12B
RR12B
RR12B
1
1
0
1
0
WR13B
RR13B
RR13B
RR13B
1
1
0
1
1
WR13A
RR13A
RR13A
RR13A
1
1
1
0
0
WR14B
RR12B
RR12B
(WR7’B)
1
1
1
0
1
WR14A
RR12B
RR12B
(WR7’B)
1
1
1
1
0
WR15B
RR13B
RR13B
RR13B
1
1
1
1
1
WR15A
RR13A
RR13A
RR13A
Notes:
1. The register names in ( ) are the values read out from that register location.
2. WR15 bit D2 enables status FIFO function (not available on NMOS).
3. WR7’ bit D6 enables extend read function (only on ESCC).
PS005308-0609
Programming