Z8523016VEG Datasheet, PDF (58/118 Pages) Zilog, Inc. – Enhanced Serial Communications Controller

Z80230/Z85230/L
Product Specification
53
Table 24. Write Register 15
Bit
7
6
5
4
3
2
1
0
R/W
W
Reset
1
1
1
1
0
0
0
0
R = Read W = Write X = Indeterminate
Bit
Position
R/W
Value Description
7
Break/Abort Interrupt Enable
6
Tx Underrun/EOM Interrupt Enable
5
CTS Interrupt Enable
4
Sync/Hunt
3
DCD Interrupt Enable
2
SDLC FIFO Enable
1
Zero Count Interrupt Enable
0
WR7’ SDLC Feature Enable
Read Registers
The ESCC contains ten read registers (eleven, counting the receive buffer RR8) in each
channel. Four of these may be read to obtain status information (RR0, RR1, RR10, and
RR15).
Two registers, RR12 and RR13, are read to learn the BRG time constant. RR2 contains
either the unmodified interrupt vector, Channel A, or the vector modified by status infor-
mation, Channel B.
RR3 contains the Interrupt Pending (IP) bits for Channel A.
RR6 and RR7 contain the information in the SDLC Frame Status FIFO, but is only read
when WR15 bit 2 is 1. If WR7’ bit 6 is 1, Write Registers WR3, WR4, WR5, and WR10
can be read as RR9, RR4, RR5, and RR14, respectively. Table 25 on page 54 through
Table 40 on page 69 list the format of the read registers.
PS005308-0609
Programming