Z8523016VEG Datasheet, PDF (12/118 Pages) Zilog, Inc. – Enhanced Serial Communications Controller

Z80230/Z85230/L
Product Specification
7
CS0 (Chip Select 0 (Input, Active Low))—This pin is latched concurrently with the
addresses on A7-A0 and must be Low for the intended bus transaction to occur.
CS1 (Chip Select 1 (Input, Active High))—This second chip select pin must be High
before and during the intended bus transaction.
DS (Data Strobe (Input, Active Low))—This pin provides timing for the transfer of data
into and out of the Z80230. If AS and DS are both Low, this condition is interpreted as a
RESET.
AS (Address Strobe (Input, Active Low))—Addresses on A7-A0 are latched by the ris-
ing edge of this signal.
PS005308-0609
Pin Descriptions