Z8523016VEG Datasheet, PDF (76/118 Pages) Zilog, Inc. – Enhanced Serial Communications Controller

Z80230/Z85230/L
Product Specification
71
Z80230 Read Cycle Timing
The Read Cycle Timing for the Z80230 is displayed in Figure 18. The register address on
A7-A0, as well as the state of CS0 and INTACK, are latched by the rising edge of AS.
R/W must be High before DS falls to indicate a Read cycle. The Z80230 data bus drivers
are enabled while CS1 is High and DS is Low.
AS
CS0
INTACK
A7–A0
Address
Data Valid
R/W
CS1
DS
Figure 18. Z80230 Read Cycle Timing
Z80230 Interrupt Acknowledge Cycle Timing
The Interrupt Acknowledge cycle timing for the Z80230 is displayed in Figure 19 on page
72. The address on A7-A0 and the state of CS0 and INTACK are latched by the rising -
edge of AS. However, if INTACK is Low. The address on A7-A0, CS0, CS1, and R/W
are ignored for the duration of the interrupt acknowledge cycle.
The Z80230 samples the state of INTACK on the rising edge of AS, and AC parameters.
Parameters 7 and 8 of Table 45 on page 83, specify the setup and hold time requirements.
Between the rising edge of AS and the falling edge of DS, the internal and external daisy
chains settle, as specified in parameter 29. A system with no external daisy chain provides
the time priority internal to the ESCC. Systems using an external daisy chain must refer to
Note 5 of Table 45, for the time required to settle the daisy chain.
If there is an interrupt pending in the ESCC, and IEI is High when DS falls, the acknowl-
edge cycle is intended for the ESCC. Consequently, the Z80230 sets the Interrupt Under
Service (IUS) latch for the highest priority pending interrupt, and places an interrupt vec-
PS005308-0609
Z80230 Interface Timing