Z8523016VEG Datasheet, PDF (78/118 Pages) Zilog, Inc. – Enhanced Serial Communications Controller

Z80230/Z85230/L
Product Specification
73
from the falling edge of WR or RD in the first transaction involving the ESCC, to the fall-
ing edge of WR or RD in the second transaction. This time must be at least four PCLKs
regardless of which register or channel is accessed.
Z85230/L Read Cycle Timing
Figure 20 displays Read Cycle timing. Addresses on A/B and D/C and the status on
INTACK must remain stable throughout the cycle. The effective RD time reduces if CE
falls after RD falls, or if it rises before RD rises.
A/B, D/C
Address Valid
INTACK
CE
D7–D0
Data Valid
RD
Figure 20. Read Cycle Timing (Z85230/L)
Z85230/L Write Cycle Timing
Figure 21 on page 74 displays Write Cycle timing. Addresses on A/B and D/C and the sta-
tus on INTACK must remain stable throughout the cycle. The effective WR time reduces
if CE falls after WR falls, or if it rises before WR rises. In Write Cycle timing, the WR sig-
nal returns a High slightly before the Address goes invalid.
Because many popular CPUs do not guarantee that the databus is valid when WR is Low,
the ESCC no longer requires a valid databus when the WR pin is Low. For more informa-
tion, see AC characteristics parameter 29 available in Table 47 on page 90.
PS005308-0609
Z80230 Interface Timing