Z8523016VEG Datasheet, PDF (116/118 Pages) Zilog, Inc. – Enhanced Serial Communications Controller

Z80230/Z85230/L
109
write cycle timing,Z85230 74
Z80230 pin assignments 3
Z80230 pin functions 2
Z85230 pin assignments 3
Z85230 pin functions 2
digital phase-locked loop 5, 19
DPLL counter Tx clock source 27
E
encoding, data 20
end of poll (EOP) character 18
enhancements
receive FIFO, 8 bytes 22
transmit FIFO, 4 bytes 22
Z80230 and Z85230 22
EOP 18
errata 99
ESCC
programming 32
read registers 53
write registers 32
external synchronization 4
F
FIFO
anti-lock feature 31
enable/disable 30
read operation 30
write operation 31
functional description 8
G
general timing characteristics table, Z80230 82
general timing table, Z85230 95
I
identification, device types 24
IE 12
input/output capabilities 9
INTACK 13
interface timing, Z80230 70
internal synchronization 4
interrupt acknowledge cycle timing
Z80230 71
Z85230 74
interrupts 12
external/status 13, 14
interrupt cknowledge (INTACK) 13
interrupt enable (IE) 12
interrupt on all receive characters or special re-
ceive conditions 14
interrupt on first receive character or special re-
ceive condition 14
interrupt on special receive conditions only 14
interrupt pending (IP) 12, 13
interrupt under service (IUS) 12, 13
receive 13
receive character available 22
transmit 13
transmit buffer empty 22, 24
Tx underrun/EOM 28
IUS latch 28
IUS problem
description 99
solutions 100
L
latch
ISU 28
RR0 27
TxIP 26
local loopback 21
M
mark idle 26
mode
1x 18
asynchronous receive 4
auto echo 21
request on transmit 24
SDLC 17
PS005308-0609
PRELIMINARY
Index