Z8523016VEG Datasheet, PDF (33/118 Pages) Zilog, Inc. – Enhanced Serial Communications Controller

Z80230/Z85230/L
Product Specification
28
Software Interrupt Acknowledge
The Z80230/Z85230/L interrupt acknowledge cycle can be initiated using software. If
Write Register 9 (WR9 bit 5 is 1), Read Register 2 (RR2) results in an interrupt INTACK
cycle, a software acknowledgment causes the INT pin to go High. The IEO pin goes Low.
The Interrupt Under Service (IUS) latch is set to the highest priority pending interrupt.
When a hardware INTACK signal is desired, a software acknowledge cycle requires that a
Reset Highest IUS command be issued in the ISR. If RR2 is read from Channel A, the
unmodified vector is returned. If RR2 is read from Channel B, then the vector is modified
to indicate the source of the interrupt. The Vector Includes Status (VIS) and No Vector
(NV) bits in WR9 are ignored when WR9 bit 5 is set to 1.
If the INTACK and IEI pins are not used, they are pulled up to V_CC through a resistor 
(2.2 k?, typical).
Fast SDLC Transmit Data Interrupt Response
To facilitate the transmission of back-to-back SDLC frames with a single shared flag
between frames, the ESCC allows data for a second frame to be written to the transmit
FIFO after the Tx Underrun/EOM interrupt occurs. This feature allows application soft-
ware more time to write the data to the transmitter while allowing the current frame to
conclude with CRC and flag. The SCC required that data not be written to the transmitter
until a TBE interrupt is generated after the CRC completed transmission.
If data is written to the transmit FIFO after the Transmit Underrun/EOM interrupt is issued
but before the TBE interrupt is issued, the Automatic EOM Reset function is enabled
(WR7’ bit 1 is 1). Consequently, the commands Reset Tx/Underrun EOM Latch and Reset
Tx CRC Generator must never be used.
SDLC FIFO Frame Status Enhancement
When used with a DMA controller, the ESCC SDLC Frame Status FIFO enhancement
maximizes the ESCC’s ability to receive high-speed, back-to-back SDLC messages. It
minimizes frame overruns due to CPU latencies in responding to interrupts. The feature
(displayed in Figure 15 on page 29) includes:
• 10-bit deep by 19-bit wide status FIFO
• 14-bit receive byte counter
• Control logic
The 10 x 19 bits status FIFO is separate from the 8-byte receive data FIFO.
When the enhancement is enabled, the status in Read Register 1 (RR1) and byte count for
the SDLC frame are stored in the 10- x 19-bit status FIFO. This action allows the DMA
PS005308-0609
Z80230/Z85230/L Enhancements