Z8523016VEG Datasheet, PDF (13/118 Pages) Zilog, Inc. – Enhanced Serial Communications Controller

Z80230/Z85230/L
Product Specification
8
Functional Description
The architecture of the ESCC is described based on its functionality as a:
• Data communications device, which transmits and receives data in a wide variety of
protocols
• Microprocessor peripheral, in which the ESCC offers valuable features such as
vectored interrupts and DMA support
The details of the communication between the receive and transmit logic of the system bus
are displayed in Figure 5 and Figure 6 on page 9. The features and data path for each of
the ESCC A and B channels are identical. For more information on SCC/ESCC and ISCC
Family of Products, refer to the respective User Manuals available for download from
www.zilog.com.
Internal Data Bus
to Other Channel
WR7
WR6
SYNC Register SYNC Register
20-Bit TX Shift Register
WR8
TX FIFO
4 Bytes _{Internal TXD}
Final Tx
MUX
TXD
Zero Insert
CRC-SDLC
CRC-Gen
ASYNC
SYNC
SDLC
Transmit
MUX and
2 Bit Delay
NRZI Encode
Transmit Clock
From Receiver
Figure 5. ESCC Transmit Data Path
PS005308-0609
Functional Description