Z8523016VEG Datasheet, PDF (35/118 Pages) Zilog, Inc. – Enhanced Serial Communications Controller

Z80230/Z85230/L
Product Specification
30
When a flag is received at the end of an SDLC frame, the frame byte count from the 14-bit
counter and 5 status bits are loaded into the status FIFO for verification by the CPU. The
CRC checker is automatically reset in preparation for the next frame, which starts immedi-
ately.
Because the byte count and status are saved for each frame, the message integrity can be
verified at a later time. Status information for up to ten frames is stored before a status
FIFO overrun occurs.
If a frame is terminated with an Abort command, the byte count and status is loaded to
the status FIFO and the counter is reset for the next frame.
FIFO Enable/Disable
This FIFO buffer is enabled when WR15 bit 2 is 1 and the ESCC is in the SDLC/HDLC
mode. Otherwise, the status register contents bypass the FIFO and transfer directly to the
bus interface (the FIFO pointer logic is reset either when disabled or by a channel or
power-on reset). When the FIFO mode is disabled, the ESCC is downward-compatible
with the NMOS Z8030/Z8530. The FIFO mode is disabled on power-up (WR15 bit 2 set
to 0 on reset). The effects of backward compatibility on the register set are that RR4 is an
image of RR0, RR5 is an image of RR1, RR6 is an image of RR2, and RR7 is an image of
RR3. For information on the added registers, see Read Registers on page 53. The status of
the FIFO Enable signal is read at RR15 bit 2. If the FIFO is enabled, the bit is set to 1; oth-
erwise it is reset to 0.
FIFO Read Operation
When WR15 bit 2 is 1 and the FIFO is not empty, the next read status register RR1 or the
additional registers RR7 and RR6, reads the FIFO. Reading status register RR1 causes one
location of the FIFO to empty, so status is read after reading the byte count; otherwise the
count is incorrect. Before the FIFO underflows, it is disabled. In this case, the multiplexer
is switched to allow status to read directly from the status register. In this state, reads from
RR7 and RR6 are undefined bit 6 of RR7 (FIFO data available) status data is coming from
the FIFO or directly from the status register, because it is set to 1 whenever the FIFO is not
empty.
Since all status bits are not stored in the FIFO, the All Sent, Parity, and EOF bits bypass
the FIFO. The status bits sent through the FIFO are the three Residue Bits, Overrun, and
CRC Error.
The correct sequence for polling the byte count and FIFO logic is RR7, RR6, then RR1
(reading RR6 is optional). Additional logic prevents the FIFO from emptying by multiple
reads from RR1. The read from RR7 latches the FIFO empty/full status bit (bit 6) and
steers the status multiplexer to read the ESCC megacell instead of the status FIFO
PS005308-0609
Z80230/Z85230/L Enhancements