Z8523016VEG Datasheet, PDF (36/118 Pages) Zilog, Inc. – Enhanced Serial Communications Controller

Z80230/Z85230/L
Product Specification
31
(because the status FIFO is empty). The read from RR1 allows an entry to be read from the
FIFO (if the FIFO is empty, the logic prevents a FIFO underflow condition).
FIFO Write Operation
When the end of an SDLC frame is received and the Status FIFO is enabled, the contents
of the status and byte-count registers load into the FIFO. The EOF signal increments the
FIFO. If the FIFO overflows, the RR7 bit 7 (FIFO overflow) is set, indicating the over-
flow. This bit and the FIFO control logic is reset by disabling and re-enabling the FIFO
control bit (WR15 bit 2). For details about FIFO control timing during an SDLC frame,
see Figure 16.
01234567
F A D D D D CC F
01234567 0
F ADDDDCC F
Internal byte strobe
increments counter
Do not load
counter on
first flag.
reset byte
counter here
Reset byte
counter, then
load counter
into FIFO and
increment PTR.
Figure 16. SDLC Byte Counting Detail
Internal byte strobe
increments counter
Reset byte
counter, then
load counter
into FIFO and
increment PTR
SDLC Status FIFO Anti-Lock Feature
When the Frame Status FIFO is enabled and the ESCC is programmed for Special Receive
Condition Only (WR1 bit 4 = bit 3=1), the data FIFO is not locked when a character with
EOF status is read.When EOF status is at the top of the FIFO, an interrupt with a vector
for receive data is generated. The command Reset Highest IUS must be issued at the
end of the ISR regardless of whether an Interrupt Acknowledge cycle was executed (hard-
ware or software).
This action allows the DMA to complete the transfer of the received frame to memory,
then interrupt the CPU that a frame was completed, without locking the FIFO. Because in
the RECEIVE INTERRUPT ON SPECIAL CONDITION ONLY mode the interrupt vec-
tor for receive data is not used, it indicates that the last byte of a frame has been read from
the receive FIFO. Reading the frame status (CRC, byte count and other status stored in the
status FIFO) determines that EOF is not required.
When a character with a special receive condition other than EOF is received (receiver
overrun or parity), a special receive condition interrupt is generated after the character is
read from the FIFO and the receive FIFO is locked until the Error Reset command is
issued.
PS005308-0609
Z80230/Z85230/L Enhancements