Z8523016VEG Datasheet, PDF (105/118 Pages) Zilog, Inc. – Enhanced Serial Communications Controller

Z80230/Z85230/L
Product Specification
100
• The processor does not acknowledge this interrupt because it is servicing another
interrupt.
• The processor finishes servicing the other interrupt and uses the Reset Highest IUS
command.
• The IP bit reset corresponding to the EOF, and the EOF interrupt is lost.
IUS Problem Solutions
The following methods can be used to work around the previously described problems.
• Alternate Operating Mode–A similar operating mode can be used to achieve the same
functionality with minimum code modifications. The ESCC must operate in Receive
Interrupts on First Character and Special Condition, instead of Receive Interrupt on
Special Condition Only.
In this mode, the Anti-Lock feature is not enabled. The FIFO is locked after the last
character of a frame has been transferred, and the interrupt condition does not
disappear until after an Error Reset command is issued to the ESCC. No Reset
Highest IUS command can clear any IP bit.
• Daisy Chain– This workaround uses the following two conditions:
– The EOF interrupt is the highest priority interrupt if only one channel is used.
– Channel A is the only channel issuing interrupts.
If both conditions are satisfied, allowing nested interrupts can solve the problem.
The processor servicing an interrupt on the daisy chain must be interruptible again
from another interrupt of higher priority on that same daisy chain.
• RR7 Register–This workaround is applicable if the EOF interrupt is used only to
notify another part of the software that there has been another frame received:
– Read RR7 after issuing the Reset IUS command.
– Check bit 6 of RR7. This bit, when set, indicates that the SDLC frame FIFO con-
tains a valid frame. Although one interrupt might have been lost (IP reset) by the
Reset IUS command, bit 6 of RR7 always indicates that at least one frame is
available in the frame FIFO. If bit 6 of RR7 is 1, notify the concerned part of the
software that at least one frame is available in the frame FIFO.
When the SDLC FIFO is enabled and Receive Interrupts on Special Conditions Only is
selected, software checks that there is a Receive Character Available interrupt, which is
generated by DMA reading an EOF character, and before issuing the Reset Highest
IUS command. Otherwise, the EOF interrupt conditions are cleared by that command.
PS005308-0609
Z80230/Z85230/L Errata