Z8523016VEG Datasheet, PDF (79/118 Pages) Zilog, Inc. – Enhanced Serial Communications Controller

Z80230/Z85230/L
Product Specification
74
A/B, D/C
INTACK
CE
D7–D0
WR
Address Valid
Address Valid
Figure 21. Write Cycle Timing (Z85230/L)
Z85230/L Interrupt Acknowledge Cycle Timing
Figure 22 displays Interrupt Acknowledge Cycle timing. Between the time INTACK goes
Low and the falling edge of RD, the internal and external IEI/IEO daisy chains settle. If
there is an interrupt pending in the ESCC and IEI is High when RD falls, the Acknowl-
edge cycle is intended for the ESCC. In this case, the ESCC may be programmed to
respond to RD Low by placing its interrupt vector on D7–D0. It then sets the appropriate
IUS latch internally. If the external daisy chain is not used, then AC Parameter 38 is
required to settle the interrupt priority daisy chain internal to the ESCC. If the external
daisy chain is used, follow the equation in AC Characteristics Note 5 (Table 47 on
page 90) to calculate the required daisy chain settle time.
INTACK
RD
D7–D0
Vector
Figure 22. Interrupt Acknowledge Cycle Timing (Z85230/L)
PS005308-0609
Z80230 Interface Timing