Z8523016VEG Datasheet, PDF(19/118 Page) Zilog, Inc. – Enhanced Serial Communications Controller

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Z8523016VEG Datasheet, PDF (19/118 Pages) Zilog, Inc. – Enhanced Serial Communications Controller

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Z80230/Z85230/L

Product Specification

When the receiver is enabled, the CPU is interrupted in one of the following three meth-

ods:

1. Interrupt on First Receive Character or Special Receive Condition

2. Interrupt on All Receive Characters or Special Receive Conditions

3. Interrupt on Special Receive Conditions Only

If WR7â bit 3 is 1, and the Special Receive Condition is selected, the Receive character

occurs when there are four bytes available in the Receive FIFO. This is most useful in syn-

chronous applications as the data is in consecutive bytes. Interrupt on First Character or

Special Condition and Interrupt on Special Condition Only are typically used with the

BLOCK TRANSFER mode. A special Receive Condition consists of one of the follow-

ing:

â¢ Receiver Overrun

â¢ Framing error in ASYNCHRONOUS mode

â¢ EOF in SDLC mode

â¢ Parity error (optional)

The Special Receive Condition interrupt is different from an ordinary receive character

available interrupt only by the status placed in the vector during the Interrupt Acknowl-

edge cycle. In Receive Interrupt on First Character or Special Condition mode, an inter-

rupt occurs from Special Receive Conditions any time after the first receive character

interrupt.

The primary function of the External/Status interrupt is to monitor the signal transitions of

the CTS, DCD, and SYNC pins. However, an External/Status interrupt is also caused by

any of the following:

â¢ A Transmit Underrun condition

â¢ A zero count in the BRG

â¢ A detection of a Break (ASYNCHRONOUS mode)

â¢ An ABORT (SDLC mode)

â¢ An End Of Poll (EOP) sequence in the data stream (SDLC LOOP mode)

The interrupt caused by the ABORT or EOP sequence has a special feature that allows the

ESCC to interrupt when the ABORT or EOP sequence is detected or terminated. This fea-

ture facilitates the proper termination of the current message, correct initialization of the

next message, and the accurate timing of the ABORT condition by external logic in SDLC

mode. SDLC LOOP mode allows secondary stations to recognize the primary station and

regain control of the loop during a poll sequence.

PS005308-0609

Functional Description

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