Z8523016VEG Datasheet, PDF (101/118 Pages) Zilog, Inc. – Enhanced Serial Communications Controller

Z80230/Z85230/L
Product Specification
96
Table 48. Z85230/L General Timing Table (20MHz applies only to Z85230) (Continued)
8.5 MHz
10 MHz
16 MHz
20 MHz
No Symbol
16a TcRTX
Parameter
RTxC Cycle
Time
Min Max Min Max Min Max Min Max Notes
472
400
244
200
6, 7, 9
16b TxRX (DPLL) DPLL Cycle
50
50
31
31
7, 8, 9
Time Min.
17 TcRTXX
18 TwRTXh
19 TwTRXI
Crystal Osc.
125
Period
TRxC High
130
Width
TRxC Low Width 130
1000 100
120
120
1000 61
80
80
1000 61 1000 3, 9
70
5, 9
70
6, 9
20 TcTRX
TRxC Cycle
472
400
244
200
6, 7, 9
Time
21 TwEXT
DCD or CTS
200
120
70
Pulse Width
60
9
22 TwSY
SYNC Pulse
200
120
70
Width
60
9
Notes:
1. RxC is RTxC or TRxC, whichever is supplying the receive clock.
2. TxC is TRxC or RTxC, whichever is supplying the transmit clock.
3. Both RTxC and SYNC have 30 pF capacitors to ground connected to them.
4. Synchronization of RxC to PCLK is eliminated in divide by four operation.
5. Parameter applies only to FM encoding/decoding.
6. Parameter applies only for transmitter and receiver; DPLL and BRG timing requirements are identical to case
PCLK requirements.
7. The maximum receive or transmit data rate is 1/4 PCLK.
8. Applies to the DPLL clock source only. Maximum data rate of 1/4 PCLK still applies. DPLL clock must have a
50% duty cycle.
9. Units in ns.
10. Units in TcPc.
PS005308-0609
Electrical Characteristics