XC3S200A-4VQG100C Datasheet, PDF (99/132 Pages) Xilinx, Inc – Architectural and Configuration Overview

Pinout Descriptions
User I/Os by Bank
Table 78 and Table 79 indicate how the available user-I/O
pins are distributed between the four I/O banks on the
FG320 package. The AWAKE pin is counted as a
dual-purpose I/O.
Table 78: User I/Os Per Bank for XC3S200A in the FG320 Package
Package
Edge
I/O Bank Maximum I/O
I/O
All Possible I/O Pins by Type
INPUT
DUAL
VREF
Top
0
60
35
11
1
5
Right
1
64
9
10
30
7
Bottom
2
60
19
6
21
6
Left
3
64
38
13
0
5
TOTAL
248
101
40
52
23
Table 79: User I/Os Per Bank for XC3S400A in the FG320 Package
Package
Edge
I/O Bank Maximum I/O
I/O
All Possible I/O Pins by Type
INPUT
DUAL
VREF
Top
0
61
35
12
1
5
Right
1
64
9
10
30
7
Bottom
2
62
19
7
21
7
Left
3
64
38
13
0
5
TOTAL
251
101
42
52
24
Footprint Migration Differences
Table 80 summarizes any footprint and functionality
differences between the XC3S200A and the XC3S400A
FPGAs that might affect easy migration between devices
available in the FG320 package. There are three such balls.
All other pins not listed in Table 80 unconditionally migrate
between Spartan-3A devices available in the FG320
package.
The arrows indicate the direction for easy migration.
Table 80: FG320 Footprint Migration Differences
Pin Bank XC3S200A Migration XC3S400A
E13
0 N.C.
Æ
INPUT
N7
2 N.C.
Æ
INPUT
P14
2 N.C.
Æ
INPUT/VREF
DIFFERENCES
3
Legend:
Æ
This pin can unconditionally migrate from the device
on the left to the device on the right. Migration in the
other direction is possible depending on how the pin is
configured for the device on the right.
CLK
8
8
8
8
32
CLK
8
8
8
8
32
DS529-4 (v2.0) August 19, 2010
www.xilinx.com
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