XC3S200A-4VQG100C Datasheet, PDF (74/132 Pages) Xilinx, Inc – Architectural and Configuration Overview

Pinout Descriptions
VQ100 Footprint (XC3S200A)
Note pin 1 indicator in top-left corner and logo orientation.
TMS 1
TDI 2
IO_L01P_3 3
IO_L01N_3 4
IO_L02P_3 5
6
IO_L02N_3
IP_3/VREF_3 7
GND 8
IO_L03P_3/LHCLK0 9
IO_L03N_3/LHCLK1 10
VCCO_3 11
IO_L04P_3/LHCLK2 12
IO_L04N_3/IRDY2/LHCLK3 13
GND 14
IO_L05P_3/TRDY2/LHCLK6 15
IO_L05N_3/LHCLK7 16
VCCINT 17
GND 18
IO_L06P_3 19
IO_L06N_3 20
IP_3 21
VCCAUX 22
IO_L01P_2/M1 23
IO_L02P_2/M2 24
IO_L01N_2/M0 25
Bank 0
Bank 2
75 TDO
74 GND
73 IO_L06N_1
72 IO_L06P_1
71 IO_L05N_1
70 IO_L05P_1
69 GND
68 IP_1/VREF_1
67 VCCO_1
66 VCCINT
65 IO_L04N_1/RHCLK7
64 IO_L04P_1/IRDY1/RHCLK6
63 GND
62 IO_L03N_1/TRDY1/RHCLK3
61 IO_L03P_1/RHCLK2
60 IO_L02N_1/RHCLK1
59 IO_L02P_1/RHCLK0
58 GND
57 IO_L01N_1
56 IO_L01P_1
55 VCCAUX
54 DONE
53 IO_L12N_2/CCLK
52 IO_L11N_2/D1(◆)
51 IO_L12P_2/D0/DIN/MISO (◆)
200A
Figure 18: VQ100 Package Footprint - XC3S200A (Top View)
17
I/O: Unrestricted, general-purpose
user I/O
20
DUAL: Configuration pins, then
possible user I/O
2
INPUT: Unrestricted,
general-purpose input pin
23
CLK: User I/O, input, or global
buffer input
2
CONFIG: Dedicated configuration
pins
4 ^{JTAG: Dedicated JTAG port pins}
0 ^{N.C.: Not connected}
13 ^{GND: Ground}
6
VREF: User I/O or input voltage
reference for bank
6
VCCO: Output voltage supply for
bank
4
VCCINT: Internal core supply
voltage (+1.2V)
3 ^{VCCAUX: Auxiliary supply voltage}
74
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DS529-4 (v2.0) August 19, 2010