XC3S200A-4VQG100C Datasheet, PDF (17/132 Pages) Xilinx, Inc – Architectural and Configuration Overview

DC and Switching Characteristics
Table 12: DC Characteristics of User I/Os Using
Single-Ended Standards
Test
Conditions
Logic Level
Characteristics
IOSTANDARD
Attribute
LVTTL⁽³⁾
2
I_OL I_OH
(mA) (mA)
2 –2
V_OL
Max (V)
0.4
V_OH
Min (V)
2.4
4
4 –4
6
6 –6
8
8 –8
12 12 –12
16 16 –16
24 24 –24
LVCMOS33⁽³⁾ 2
4
2 –2
4 –4
0.4
V_CCO – 0.4
6
6 –6
8
8 –8
12 12 –12
16 16 –16
24⁽⁴⁾ 24 –24
LVCMOS25⁽³⁾ 2
4
2 –2
4 –4
0.4
V_CCO – 0.4
6
6 –6
8
8 –8
12 12 –12
16⁽⁴⁾ 16 –16
24⁽⁴⁾ 24 –24
LVCMOS18⁽³⁾ 2
4
2 –2
4 –4
0.4
V_CCO – 0.4
6
6 –6
8
8 –8
12⁽⁴⁾ 12 –12
16⁽⁴⁾ 16 –16
LVCMOS15⁽³⁾ 2
4
2 –2
4 –4
0.4
V_CCO – 0.4
6
6 –6
8⁽⁴⁾
8
–8
12⁽⁴⁾ 12 –12
LVCMOS12⁽³⁾ 2
2 –2
4⁽⁴⁾
4
–4
0.4
V_CCO – 0.4
6⁽⁴⁾
6
–6
Table 12: DC Characteristics of User I/Os Using
Single-Ended Standards(Continued)
Test
Conditions
Logic Level
Characteristics
IOSTANDARD
Attribute
PCI33_3⁽⁵⁾
PCI66_3⁽⁵⁾
HSTL_I⁽⁴⁾
HSTL_III⁽⁴⁾
HSTL_I_18
HSTL_II_18⁽⁴⁾
HSTL_III_18
SSTL18_I
SSTL18_II⁽⁴⁾
SSTL2_I
SSTL2_II⁽⁴⁾
SSTL3_I
SSTL3_II
I_OL I_OH
V_OL
(mA) (mA) Max (V)
V_OH
Min (V)
1.5 –0.5 10% V_CCO 90% V_CCO
1.5 –0.5 10% V_CCO 90% V_CCO
8 –8
0.4
V_CCO - 0.4
24 –8
0.4
V_CCO - 0.4
8 –8
0.4
V_CCO - 0.4
16 –16
0.4
V_CCO - 0.4
24 –8
0.4
V_CCO - 0.4
6.7 –6.7 V_TT – 0.475 V_TT + 0.475
13.4 –13.4 V_TT – 0.603 V_TT + 0.603
8.1
16.2
8
16
–8.1
–16.2
–8
–16
V_TT – 0.61
V_TT – 0.81
V_TT – 0.6
V_TT – 0.8
V_TT + 0.61
V_TT + 0.81
V_TT + 0.6
V_TT + 0.8
Notes:
1. The numbers in this table are based on the conditions set forth in
Table 8 and Table 11.
2. Descriptions of the symbols used in this table are as follows:
– I_OL the output current condition under which V_OL is tested
– I_OH the output current condition under which V_OH is tested
– V_OL the output voltage that indicates a Low logic level
– V_OH the output voltage that indicates a High logic level
– V_CCO the supply voltage for output drivers
– V_TT the voltage applied to a resistor termination
3. For the LVCMOS and LVTTL standards: the same V_OL and V_OH
limits apply for the Fast, Slow, and QUIETIO slew attributes.
4. These higher-drive output standards are supported only on
FPGA banks 1 and 3. Inputs are unrestricted. See the chapter
"Using I/O Resources" in UG331.
5. Tested according to the relevant PCI specifications. For
information on PCI IP solutions, see www.xilinx.com/pci. The
PCIX IOSTANDARD is available and has equivalent
characteristics but no PCI-X IP is supported.
DS529-3 (v2.0) August 19, 2010
www.xilinx.com
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