XC3S200A-4VQG100C Datasheet, PDF (29/132 Pages) Xilinx, Inc – Architectural and Configuration Overview

DC and Switching Characteristics
Table 22: Propagation Times for the IOB Input Path(Continued)
Symbol
T_IOPID
T_IOPLI
Description
Conditions
The time it takes for data to travel LVCMOS25⁽²⁾
from the Input pin to the I output with
the input delay programmed
The time it takes for data to travel
from the Input pin through the IFF
latch to the I output with no input
delay programmed
LVCMOS25⁽²⁾
DELAY_VALUE
5
6
7
8
9
10
11
12
13
14
15
16
IFD_DELAY_VALUE=0
T_IOPLID The time it takes for data to travel LVCMOS25⁽²⁾
1
from the Input pin through the IFF
latch to the I output with the input
2
delay programmed
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
Speed Grade
-5
-4
Device Max Max Units
XC3S1400A 3.17 3.52 ns
3.52 3.92 ns
3.82 4.18 ns
4.10 4.57 ns
3.84 4.31 ns
4.20 4.79 ns
4.46 5.06 ns
4.87 5.51 ns
5.07 5.73 ns
5.43 6.08 ns
5.73 6.33 ns
6.01 6.77 ns
XC3S50A 1.70 1.81 ns
XC3S200A 1.85 2.04 ns
XC3S400A 1.44 1.74 ns
XC3S700A 1.48 1.74 ns
XC3S1400A 1.50 1.97 ns
XC3S50A 2.30 2.41 ns
3.24 3.35 ns
3.65 3.98 ns
4.18 4.55 ns
4.02 4.47 ns
4.86 5.32 ns
5.61 6.17 ns
6.11 6.75 ns
XC3S200A 2.19 2.43 ns
2.86 3.16 ns
3.52 4.01 ns
4.02 4.60 ns
3.83 4.43 ns
4.70 5.46 ns
5.48 6.33 ns
5.99 6.94 ns
XC3S400A 1.93 2.25 ns
2.57 2.90 ns
3.16 3.66 ns
3.63 4.19 ns
DS529-3 (v2.0) August 19, 2010
www.xilinx.com
29