XC3S200A-4VQG100C Datasheet, PDF (42/132 Pages) Xilinx, Inc – Architectural and Configuration Overview

DC and Switching Characteristics
Configurable Logic Block (CLB) Timing
Table 30: CLB (SLICEM) Timing
Symbol
Description
Clock-to-Output Times
T_CKO
When reading from the FFX (FFY) Flip-Flop, the time
from the active transition at the CLK input to data
appearing at the XQ (YQ) output
Setup Times
T_AS
Time from the setup of data at the F or G input to the
active transition at the CLK input of the CLB
T_DICK
Time from the setup of data at the BX or BY input to
the active transition at the CLK input of the CLB
Hold Times
T_AH
Time from the active transition at the CLK input to the
point where data is last held at the F or G input
T_CKDI
Time from the active transition at the CLK input to the
point where data is last held at the BX or BY input
Clock Timing
T_CH
The High pulse width of the CLB’s CLK signal
T_CL
The Low pulse width of the CLK signal
F_TOG
Toggle frequency (for export control)
Propagation Times
T_ILO
The time it takes for data to travel from the CLB’s F
(G) input to the X (Y) output
Set/Reset Pulse Width
T_{RPW_CLB}
The minimum allowable pulse width, High or Low, to
the CLB’s SR input
Speed Grade
-5
-4
Min
Max
Min
Max
–
0.60
–
0.68
0.18
–
0.36
–
1.58
–
1.88
–
0
–
0
–
0
–
0
–
0.63
–
0.75
–
0.63
–
0.75
–
0
770
0
667
–
0.62
–
0.71
1.33
–
1.61
–
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8.
Units
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
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DS529-3 (v2.0) August 19, 2010