XC3S200A-4VQG100C Datasheet, PDF (56/132 Pages) Xilinx, Inc – Architectural and Configuration Overview

DC and Switching Characteristics
Table 47: Master Mode CCLK Output Frequency by ConfigRate Option Setting
Symbol
Description
ConfigRate
Setting
Temperature
Range
Minimum
F_CCLK1
F_CCLK3
F_CCLK6
F_CCLK7
Equivalent CCLK clock frequency
1
by ConfigRate setting
(power-on value)
3
6
(default)
7
F_CCLK8
8
F_CCLK10
10
F_CCLK12
12
F_CCLK13
13
F_CCLK17
17
F_CCLK22
22
F_CCLK25
25
F_CCLK27
27
F_CCLK33
33
F_CCLK44
44
F_CCLK50
50
F_CCLK100
100
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
0.400
1.20
2.40
2.80
3.20
4.00
4.80
5.20
6.80
8.80
10.00
10.80
13.20
17.60
20.00
40.00
Maximum
0.797
0.847
2.42
2.57
4.83
5.13
5.61
5.96
6.41
6.81
8.12
8.63
9.70
10.31
10.69
11.37
13.74
14.61
18.44
19.61
20.90
22.23
22.39
23.81
27.48
29.23
37.60
40.00
44.80
47.66
88.68
94.34
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Table 48: Master Mode CCLK Output Minimum Low and High Time
ConfigRate Setting
Symbol
Description
1 3 6 7 8 10 12 13 17 22 25 27 33 44 50 100 Units
Master Mode Commercial 595 196 98.3 84.5 74.1 58.4 48.9 44.1 34.2 25.6 22.3 20.9 17.1 12.3 10.4 5.3 ns
T_MCCL,
CCLK
T_MCCH Minimum Low _{Industrial 560 185 92.6 79.8 69.8 55.0 46.0 41.8 32.3 24.2 21.4 20.0 16.2 11.9 10.0 5.0 ns}
and High Time
Table 49: Slave Mode CCLK Input Low and High Time
Symbol
Description
T_SCCL,
T_SCCH
CCLK Low and High time
Min
Max
Units
5
∞
ns
56
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DS529-3 (v2.0) August 19, 2010