XC3S200A-4VQG100C Datasheet, PDF (46/132 Pages) Xilinx, Inc – Architectural and Configuration Overview

DC and Switching Characteristics
Block RAM Timing
Table 35: Block RAM Timing
Speed Grade
-5
-4
Symbol
Description
Min
Max
Min
Max
Clock-to-Output Times
T_RCKO
When reading from block RAM, the delay from the active
transition at the CLK input to data appearing at the DOUT
–
2.06
–
2.49
output
Setup Times
T_{RCCK_ADDR} Setup time for the ADDR inputs before the active transition at
the CLK input of the block RAM
0.32
–
0.36
–
T_{RDCK_DIB} Setup time for data at the DIN inputs before the active
transition at the CLK input of the block RAM
0.28
–
0.31
–
T_{RCCK_ENB} Setup time for the EN input before the active transition at the
CLK input of the block RAM
0.69
–
0.77
–
T_{RCCK_WEB} Setup time for the WE input before the active transition at the
CLK input of the block RAM
1.12
–
1.26
–
Hold Times
T_{RCKC_ADDR} Hold time on the ADDR inputs after the active transition at the
CLK input
0
–
0
–
T_{RCKD_DIB} Hold time on the DIN inputs after the active transition at the
CLK input
0
–
0
–
T_{RCKC_ENB} Hold time on the EN input after the active transition at the CLK
input
0
–
0
–
T_{RCKC_WEB} Hold time on the WE input after the active transition at the CLK
input
0
–
0
–
Clock Timing
T_BPWH
High pulse width of the CLK signal
T_BPWL
Low pulse width of the CLK signal
Clock Frequency
1.56
–
1.79
–
1.56
–
1.79
–
F_BRAM
Block RAM clock frequency
0
320
0
280
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
46
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DS529-3 (v2.0) August 19, 2010