XC3S200A-4VQG100C Datasheet, PDF (49/132 Pages) Xilinx, Inc – Architectural and Configuration Overview

DC and Switching Characteristics
Digital Frequency Synthesizer (DFS)
Table 38: Recommended Operating Conditions for the DFS
Symbol
Input Frequency Ranges⁽²⁾
F_CLKIN
CLKIN_FREQ_FX
Input Clock Jitter Tolerance⁽³⁾
CLKIN_CYC_JITT_FX_LF
CLKIN_CYC_JITT_FX_HF
CLKIN_PER_JITT_FX
Description
Frequency for the CLKIN input
Cycle-to-cycle jitter at the CLKIN
input, based on CLKFX output
frequency
Period jitter at the CLKIN input
F_CLKFX < 150 MHz
F_CLKFX > 150 MHz
Speed Grade
-5
-4
Min Max Min Max
0.200 333⁽⁴⁾ 0.200 333⁽⁴⁾
–
±300
–
±300
–
±150
–
±150
–
±1
–
±1
Units
MHz
ps
ps
ns
Notes:
1. DFS specifications apply when either of the DFS outputs (CLKFX or CLKFX180) are used.
2. If both DFS and DLL outputs are used on the same DCM, follow the more restrictive CLKIN_FREQ_DLL specifications in Table 36.
3. CLKIN input jitter beyond these limits may cause the DCM to lose lock.
4. To support double the maximum effective FCLKIN limit, set the CLKIN_DIVIDE_BY_2 attribute to TRUE. This attribute divides the incoming
clock frequency by two as it enters the DCM.
Table 39: Switching Characteristics for the DFS
Speed Grade
-5
-4
Symbol
Description
Device Min
Max
Min
Max Units
Output Frequency Ranges
CLKOUT_FREQ_FX⁽²⁾
Output Clock Jitter^(3,4)
Frequency for the CLKFX and CLKFX180 outputs
All
5
350
5
320 MHz
CLKOUT_PER_JITT_FX
Period jitter at the CLKFX and CLKFX180
outputs.
CLKIN
≤ 20 MHz
All
Typ
Max
Typ
Max
Use the Spartan-3A Jitter Calculator: ps
www.xilinx.com/support/documentatio
n/data_sheets/s3a_jitter_calc.zip
Duty Cycle^(5,6)
CLKIN
> 20 MHz
±[1% of ±[1% of ±[1% of ±[1% of ps
CLKFX CLKFX CLKFX CLKFX
period period period period
+ 100] + 200] + 100] + 200]
CLKOUT_DUTY_CYCLE_FX Duty cycle precision for the CLKFX and CLKFX180 outputs,
All
including the BUFGMUX and clock tree duty-cycle distortion
Phase Alignment⁽⁶⁾
±[1% of
±[1% of ps
–
CLKFX
period
–
CLKFX
period
+ 350]
+ 350]
CLKOUT_PHASE_FX
Phase offset between the DFS CLKFX output and the DLL
CLK0 output when both the DFS and DLL are used
All
–
±200
–
±200 ps
CLKOUT_PHASE_FX180
Phase offset between the DFS CLKFX180 output and the DLL All
CLK0 output when both the DFS and DLL are used
±[1% of
±[1% of ps
–
CLKFX
period
–
CLKFX
period
+ 200]
+ 200]
DS529-3 (v2.0) August 19, 2010
www.xilinx.com
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