XC3S200A-4VQG100C Datasheet, PDF (22/132 Pages) Xilinx, Inc – Architectural and Configuration Overview

DC and Switching Characteristics
I/O Timing
Pin-to-Pin Clock-to-Output Times
Table 18: Pin-to-Pin Clock-to-Output Times for the IOB Output Path
Symbol
Description
Conditions
Clock-to-Output Times
T_ICKOFDCM
When reading from the Output
Flip-Flop (OFF), the time from the
active transition on the Global
Clock pin to data appearing at the
Output pin. The DCM is in use.
LVCMOS25⁽²⁾, 12mA
output drive, Fast slew
rate, with DCM⁽³⁾
T_ICKOF
When reading from OFF, the time
from the active transition on the
Global Clock pin to data appearing
at the Output pin. The DCM is not
in use.
LVCMOS25⁽²⁾, 12mA
output drive, Fast slew
rate, without DCM
Device
XC3S50A
XC3S200A
XC3S400A
XC3S700A
XC3S1400A
XC3S50A
XC3S200A
XC3S400A
XC3S700A
XC3S1400A
Speed Grade
-5
-4
Max
Max
Units
3.18
3.42
ns
3.21
3.27
ns
2.97
3.33
ns
3.39
3.50
ns
3.51
3.99
ns
4.59
5.02
ns
4.88
5.24
ns
4.68
5.12
ns
4.97
5.34
ns
5.06
5.69
ns
Notes:
1. The numbers in this table are tested using the methodology presented in Table 27 and are based on the operating conditions set forth in
Table 8 and Table 11.
2. This clock-to-output time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or a
standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. If the former is true, add the appropriate
Input adjustment from Table 23. If the latter is true, add the appropriate Output adjustment from Table 26.
3. DCM output jitter is included in all measurements.
22
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DS529-3 (v2.0) August 19, 2010